Is this the right way of implementing fsm

[streetHawkk]

Dear Friends,

I need your expert advise in designing my state machine. I would like to understand if it is a
good practice to perform some complex computation inside states in the statemachine.


for eg:

pseudocode

---

Code VHDL - [expand]
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statedecoder: process(currState, inputval ....)
begin
 
 case currState:
    when STATE_1:
        -- do some complex computations
        -- like multiplication & addition etc and this state
        -- would not change for several 100clk cycles.
 
 
 
    when STATE_2:
              -- similar to the above state.
 
    ...
    ..

---

Please comment. If this approach is not good then please suggest a better way to implement such cases.

Thanks in advance.
HwK

 

[vipinlal]

See this example:

https://vhdlguru.blogspot.in/2010/04/how-to-implement-state-machines-in-vhdl.html

 

[TrickyDicky]

I assume there would be a second process to handle the registering of the state machine? this process will just create a load of combinatorial logic - so it wont care that something wont change for 1000s of clock cycles - there is no clock involved, so it not used.

This is too small an example to really understand what you are trying to do. THe two process state machine is a standard way of writing a state machine, and there are many examples around on the web. The problem with them is they can be prone to latches if you do not assign every signal in every case. Using a single process state machine is not prone to these problems.

 

[mrflibble]

Google "sunburst design fsm" for some good papers on FSM.

 

[streetHawkk]

In continuation to the FSM, what is the maximum number of states that a state machine can have, my current design runs with more than 50 states, Will this have any implications.

Please comment.

 

[rberek]

There is no maximum number. If the FPGA or ASIC has enough resources for the larger logic and you can meet timing, you can have as many states as you want.

r.b.

 

[streetHawkk]

Thanks for the response, For such a big state machine, can i still stick to one-hot encoding or should i leave it upto the synthesizer to suitably select my state machine encoding method.

 

[rberek]

50 states is not a really large number. That's only a 6-bit state register if you don't one-hot encode and 50 if you do. In my opinion, FWIW, you also have to consider what is performed in each state and the complexity of the logic that decides the next state. You can make a 1000 state FSM where each state does nothing but transition to the next state and have no issues. You can write a 10-state FSM that performs many complex functions in each state and has complicated state transition logic and that might give you problems.

I generally let the tool do its thing and if there are issues, I make adjustments as necessary. Just my opinion, however.

r.b.

 

[TrickyDicky]

But you also have to think about complexity. Is 50 states neccesary - is it easy for the next engineer to understand? is it well commented?