[SOLVED] Is this possible in xilinx..?

[Sasi Cm]

module encc(a,b,c,clk,temp);
input [0:50]a;
input clk;
output [0:25]b;
reg [0:25]b;
output [0:4]temp;
assign c=a[0:4];
always @ (posedge clk)
begin
assign temp=c^a[5:9];
if(temp[0]!=1&&temp[1]!=1&&temp[2]!=1&&temp[3]!=1&&temp[4]!=1)
begin
c<=00;
end
else if(temp[0]!=0&&temp[1]!=0&&temp[2]!=0&&temp[3]!=0&&temp[4]!=0)
begin
c<=10;
end
else
begin
c<=11;
end
end
endmodule

 

[FvM]

It's not possible in Verilog, several rules are violated.
e.g. c undefined, multiple drivers for c, assign statement in always block