hcu
Advanced Member level 4
Hello all,
I am new to this altera stuff started working on s10 device.
I am showing you a screenshot consists of
1. Hard IP of pcie gen3 for s10
2. onchip mem
3. nios 2 processor
4. jtag uart
5. emif (ddr3)
I want first to access both onchip ram and ddr3 from nios eclispe sdk. and later i want to access those locations from computer via pcie .
something going wrong and unable to do read/write ocm and ddr from SDK. In both memories (2 bars) ,im able to access only ocm (bar0) from the computer driver and application code.
here also , there is one more issue . my ocm is 256 kb and ddr3 is 256mb but the command "dmsg" showing double the memory size i.e 512kb for ocm and 512mb for ddr3.
i want to know anything wrong with the soc integration in qsys platform designer. one can see that , im connecting ddr3 clock output and reset output connected to all other peripherals and im leaving pcie clock out unconnected.
regards,
Anil k
I am new to this altera stuff started working on s10 device.
I am showing you a screenshot consists of
1. Hard IP of pcie gen3 for s10
2. onchip mem
3. nios 2 processor
4. jtag uart
5. emif (ddr3)
I want first to access both onchip ram and ddr3 from nios eclispe sdk. and later i want to access those locations from computer via pcie .
something going wrong and unable to do read/write ocm and ddr from SDK. In both memories (2 bars) ,im able to access only ocm (bar0) from the computer driver and application code.
here also , there is one more issue . my ocm is 256 kb and ddr3 is 256mb but the command "dmsg" showing double the memory size i.e 512kb for ocm and 512mb for ddr3.
i want to know anything wrong with the soc integration in qsys platform designer. one can see that , im connecting ddr3 clock output and reset output connected to all other peripherals and im leaving pcie clock out unconnected.
regards,
Anil k