compile options in modelsim
Hi,
As already mentioned in the answers above, it may be the problem of VHDL version. In Modelsim default version is VHDL-87. If you are using syntax from VHDL-93 you have to set this version in Modelsim. There are two-three methods to set this option but altimate aim is the same:
1. Go to "Compile" menu and select "Compile Options". There select VHDL and check box for "Use 1993 Language Syntax".
2. You can directly set this option by modifying "modelsim.ini" file in your simulation folder. You can write following line in this file:
VHDL93 = 1
3. If you are using compile macro (TCL) you can mention different compile option for different module as:
vcom $optimize -93 -reportprogress 300 -work work file1.vhd
vcom $optimize -87 -reportprogress 300 -work work file2.vhd
.
.
.
so file1 will be compiled using 93 syntax and file2 using 87 syntax.
I have tried to make this one point clear. In case you are facing some other problem feel free to post it.
Regards,
Jitendra