[SOLVED] Is there any way to define some synthesizable thing, solely for simulation in VHDL

[syedshan]

Hi

As the name suggest.
I have introduced some testing signals in my design. But I intend them only for simulation.
For example there are around 20 signals of type bit array and they help in debugging, but I do not need them to be synthesized since they might take space or may also affect the clock somewhat..

Is there any way to define them only as non-syntheziable thing.

Thanks

 

[FvM]

It's usually done with synthesis translate_off and translate_on directives, check your tools manual.

 

[syedshan]

Thanks got it

 

[TrickyDicky]

if they are not connected to any outputs, they shouldnt cause a problem as they will be synthesised away, unless they are completly unsynthesisable. Still, the translate_on/off helps other engineers out too..

 

[syedshan]

if they are not connected to any outputs, they shouldnt cause a problem as they will be synthesised away, unless they are completly unsynthesisable. Still, the translate_on/off helps other engineers out too..

Hi!!

Is this some sort of riddle, since I cannot get it
can you explain a little

 

[TrickyDicky]

if you wrote this

signal some_reg :  std_logic;

...inside clocked process
some_reg <= input;

and some_reg was not connected to the output in any way, the synthesisor will just remove it. You can use attributes to keep it, which can be handy for debug signals in chipscope/signaltap

but if you write this

process(a,b,c)
begin
wait until rising_edge(a);
echo("THis is a debug");

wait until falling_edge(b);
some_sig <= input;

wait on c;
end process

You would need to wrap --synthesis translate_off/on around it, because the synth would choke on it.

 

[syedshan]

ok.
Thank you will keep in mind.