Is there any difference between std_logic and std_logic_vector in VHDL?

[vinodkumar]

Hi
Is there any difference between std_logic and std_logic_vector(0 downto 0);

thanks and regards
vinod.

 

[avimit]

Re: VHDL-doubt

Physically No, logically Yes.
Suppose a function say add_one(in : std_logic_vector) return std_logic_vector; takes in a parameter of type 'std_loigc_vector', adds '1' to it and returns an 'std_loigc_vector'. Now suppose you want to add '1' to 1 bit binary number, and you are using this 'add_one' function. Then If there is no difference between 'std_logic_vectr(0 downto 0)' and 'std_logic' then you can easily pass either of the two to the function. But you cannot do that. you will have to pass the '1' bit binary number as std_logic_vector(0 downto 0) and not as 'std_logic'. So there is a difference.
Kr,
Avi
http://www.vlsiip.com

 

[vomit]

Re: VHDL-doubt

According to the VHDL language standard:

The first is a scalar type.

The second is an array of a scalar type, even if it only has one element.

Compare to C:

char c;
char arr[1];

where c is a character, and arr is an array of 1 character, to be used as arr[0] if you want to make it behave as a char.

It's exactly the same in VHDL.

 

[YenYu]

Re: VHDL-doubt

Yes, there's an different.
Std_logic is used for rather a '1' or '0'
But Std_logic_vector(10 downto 0) is used for binarys or a string of nos.

 

[nag123]

Re: VHDL-doubt

thanks avimith. now i understood the difference.