is there additional mask (cost) needed if we use diode in a CMOS process?

[alex2013]

Hi,
I have another question regarding diode and RFID.
What is the reason people use MOSFETS as diode in rectifier of RFID (I've noticed it in some papers), instead of just using diode? Is it the to reduce the mask cost? or are there any other reasons?

Also, will using diode actually means addional mask (cost) needed? cant they created by just the same mask/process used to create MOSFETS?

 

[dick_freebird]

A MOS diode will have zero recovery time because it is all
majority carrier (provided you don't push any of the parasitic
diodes into forward conduction). They also can be gate-
commutated making them "more ideal" - important when you
are dealing with signals of very low amplitude that might not
even ***** a PN diode "on".

"Freebie" diodes often have unfortunate size, connectivity
limits and tend to not be characterized very well for stuff
like reverse recovery time (which could allow most or all of
your forward-harvested-charge to slosh right back out of
the reservoir).

A diode which has both terminals "free", in a JI process, must
be in a well (or nested wells). This means it's really a BJT that
you hope stays in cutoff, and has large stray capacitance at
some (possibly invisible) "terminals".

You should have at least two types of possible, zero cost but
fairly poorly modeled and controlled, diodes in any JI CMOS
technology. There may be "better" ones in a twin-well flow,
but whether these are actually better for the use, you'd have
to judge for yourself. The extra well is extra cost, of course.

 

[alex2013]

Thank you dick_freebird for your reply.
Your comment about not pushing the parasitic diodes into forward bias makes me think:

Do you have any opinion about using PMOS as a diode, but with the backgate connected to the gate and drain (assuming the PMOS diode is in forward bias).
During forward bias of the PMOS diode, this will mean forward body bias (backgate connected to drain), which reduce the threshold voltage hence reduce the turn on voltage of the PMOS diode. During reverse bias (of the PMOS diode), the backgate will be connected to source hence operating as a normal PMOS diode.
Will it also benefit from zero recovery time in this configuration?

I see only good things in this configuration, but I've never seen anyone use it in papers or articles.
Can you tell me why?

People usually connect the gate to drain and backgate to the source (assuming the PMOS diode is in forward bias). I think this will mean when the PMOS diode is in reverse bias, backgate will be connected to drain, hence source-backgate pn junction will be forward biased and leakage current flows. This defeat its meaning as a diode.

Thanks in advance.

A MOS diode will have zero recovery time because it is all
majority carrier (provided you don't push any of the parasitic
diodes into forward conduction). They also can be gate-
commutated making them "more ideal" - important when you
are dealing with signals of very low amplitude that might not
even ***** a PN diode "on".

"Freebie" diodes often have unfortunate size, connectivity
limits and tend to not be characterized very well for stuff
like reverse recovery time (which could allow most or all of
your forward-harvested-charge to slosh right back out of
the reservoir).

A diode which has both terminals "free", in a JI process, must
be in a well (or nested wells). This means it's really a BJT that
you hope stays in cutoff, and has large stray capacitance at
some (possibly invisible) "terminals".

You should have at least two types of possible, zero cost but
fairly poorly modeled and controlled, diodes in any JI CMOS
technology. There may be "better" ones in a twin-well flow,
but whether these are actually better for the use, you'd have
to judge for yourself. The extra well is extra cost, of course.