Thanks again for the reply.
If it does not work, I have a real problem to implement what I want to do now.
Let me explain what I wanted to do:
The design requires a FIFO with data_width=32 (Dword) and certain depth. It is required that each time when enqueue is '1', one or more DWs are written into the FIFO. the number of DW written in the same cycle is decided by an input signal "wr_size".
(Note that the FIFO is based not on ram, but registers.)
Since the number of valid DW is not controllable and not predictable, I think I need some logic like:
"
Code Verilog - [expand] |
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| reg [31:0] mem [0:128];
wire [31:0] input_DW[0:7];
wire [2:0] wr_size;
mem[wr_start_addr][31:0] <= input_DW[0][31:0];
mem[wr_start_addr+1][31:0] <= input_DW[1][31:0];
//....
mem[wr_start_addr+wr_size-1][31:0] <= input_DW[wr_size-1][31:0]; |
"
So how to implement the idea into something synthesizable?
Or, can I generate a input_DW_valid[0:7] to indicate which DW needs to be written into the FIFO?
something like:
"
Code Verilog - [expand] |
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| always_comb
begin
for(int i=0; i<8; i++)
if(i<wr_size)
input_DW_valid[i] = 1'b1;
else
input_DW_valid[i] = 1'b0;
end
//...
always_ff@(posedge clk, negedge rstb)
begin : buffer_write
if(! rstb) begin
for (int i=0; i<128; i=i+1) mem[i] <= 32'b0;
end
else begin
for(int i=0; i<8; i++)
if(input_DW_valid[i] == 1'b1)
mem[wr_start_addr+i][31:0] <= input_DW[i][31:0];
end |
"
Will it work?
Thanks a lot!
No, it's still trying to generate or not generate logic after you've already synthesized the hardware (runtime)