I posted a similar question on xilinx forum, however I know this forum and community is much more informative and responsive.
The goal it to create a configurable gpio pad ring for an fpga design. A package file contains the information for GPIO_TC_DIR and GPIO_TC_TYPE, which are the conditions used in a generate statement to determine which io buffer is instantiated.
--vhdl08
gpio_type :If diff_type :(GPIO_TC_TYPE(I)= Differential)Generatebegin
gpio_dir :case GPIO_TC_DIR(I)generatewhen c1: input_only =>begin
gpio_tc_ibuf : IBUFDS
genericmap(
iostandard =>"BLVDS_25")PortMap(
O => GPIO_T_IN(I),
I => GPIO_T(I),
IB => GPIO_C(I));
GPIO_C_IN(I)<= '0';end c1;--End Generate ip; elsif op : (GPIO_TC_DIR(I) = Output_Only) Generatewhen c2 : output_only =>begin
gpio_tc_obuf: OBUFDS
genericmap(
iostandard =>"BLVDS_25")PortMap(
I => GPIO_T_OUT_int(I),
O => GPIO_T(I),
OB => GPIO_C(I));
GPIO_T_IN(I)<= '0';
GPIO_C_IN(I)<= '0';end c2;endgenerate
gpio_dir;end diff_type;elsif se_type :(GPIO_TC_TYPE(I)= single_ended)generatebegin
gpio_t_iobuf : iobuf
genericmap(
iostandard =>"LVCMOS25")portmap(
i => gpio_t_out_int(i),
t => gpio_t_op_enb(i),
o => gpio_t_in(i),
io => gpio_t(i));
gpio_c_iobuf : iobuf
genericmap(
iostandard =>"LVCMOS25")portmap(
i => gpio_c_out_int(i),
t => gpio_c_op_enb(i),
o => gpio_c_in(i),
io => gpio_c(i));end se_type;endgenerate gpio_type;
I'm at home now so I can't check whats available in the language template. Does anyone know of a better component I should use? (note configuring the xdc to have the values defeats the purpose of the generate & generics)
attribute iostandard of gpio_t(I):signalis LVDS_25;
Can't identify the signal.
"attribute iostandard : string" seems happy being placed in block declarative part/item {xxx}
Code VHDL - [expand]
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generate--xxxattribute IOSTANDARD :string;attribute IOSTANDARD of GPIO_T(I):signalis"LVDS_25";attribute IOSTANDARD of GPIO_C(I):signalis"LVDS_25";begin
I was not able to get attribute method working with a generate statement.
I can get away with using a bespoke constraints .xdc file per design. However the plan was to use a purely hdl solution for xilinx, where the configuration & package variables determined the input output voltage standards for certain gpio pins.