is there a limitation to paralleling MOS current sources?

[treehugger]

hi,
in my design, i figured out that i need a large array of current sources (maybe a thousand of them or more). is there any limitation, drawback of paralleling so many current sources?

thanks in advance.

 

[aomeen]

Re: is there a limitation to paralleling MOS current sources

I wonder if you can mension the specific application, do you need them for bias, or for DAC or what ??

But generally speaking...

You need to make them multiples of a unit cell in order to ensure matching between them, When they become very large, you need to care in the layout to make them to ensure process spread, common centroid and interdegitation are examples of layout matching tricks

 

[Mistico_Pereyra]

Re: is there a limitation to paralleling MOS current sources

I imagine you have a very large transistor as a current source. You have to split the transistor and as aomeen says, you can use techniques as common centroid and interdegitation to layout the transistor and achieve a good matching, thats is a better option instead of paralleling courrents souces!!

 

[treehugger]

Re: is there a limitation to paralleling MOS current sources

I wonder if you can mension the specific application, do you need them for bias, or for DAC or what ??

But generally speaking...

You need to make them multiples of a unit cell in order to ensure matching between them, When they become very large, you need to care in the layout to make them to ensure process spread, common centroid and interdegitation are examples of layout matching tricks

thanks for replying.

actually i am going to design a DAC. since monotonicity is important for me i decided to include as little resistors as possible (maybe non), and that implies big arrays of unit cell current sources.

..so, among these layout techniques you have mentioned, which one is suitable for a chip size of (10µm-1mm)? i think common centroid wont work.

 

[eezou]

Matching is the most important. You can draw layout carefully.

 

[jonrhan]

Re: is there a limitation to paralleling MOS current sources

I think you will have issues with so many, regardless of resistors or transistors. This is why so many folks are suggesting interdigitation. Remember that matching is usually only good within about several transistors, so process variation is a large factor in what you are proposing for match. Very tough to make thousands of current sources/loads and expect them to match to less than 1%. With that number, I would be surprised if you achieved less than 10% mismatch across the outputs. And this would also be if you buffered the gates! TOUGH!!! Interdigitation is definitely the way to go if you are to have any chance in succeeding.