Delay Element?
Yes, some Xilinx FPGAs provide adjustable IDELAY and IODELAY primitives in the device's I/O blocks. They are most often used to make small adjustments to I/O timing, but with some imagination you can find other creative uses. For details, refer to your FPGA User Guide, and the special ISE Libraries Guide for your specific FPGA.
Those delays require instantiation of special library primitives. They are not accessible from the common delay statements in Verilog or VHDL.