your input has 4 bits.
If you divide it by 8 you are shifting 3 times, so, the result is 000e_xk[3]
This last value could be 1 or 0, and then is always minor than 2.
This is the reason why you are getting always a 0.
with 4 bits the max dec value that you can obtain is 15, divided by 8 is always minor than 2. I think that you want a 16 dec value in your input. In that case, your input has to have 5 bits.
Did you declare e_xk1 as an output earlier on in the module? Can't tell from your code...
So maybe make it:
Code:
input [3:0] r;
output reg e_xk1;
etc...
Or you could just do:
Code:
input [3:0] r;
output e_xk1; // note the lack of register
assign e_xk1 = r[3]; // since all you are doing is divide by 8 == shift by 3.
Did you intend the output e_xk1 to be a combinatorial? Or is the registered approach wanted but the clock is missing? Possibly **broken link removed** or **broken link removed** might clarify things. You might also want to google "verilog combinatorial vs sequential".
assign e_xk1 = r[3]; // since all you are doing is divide by 8 == shift by 3.
but it gives e_xk1=1 only when r=8.....when r is less than 8 e.g r=7 it gives 0
i want that when r is greater than 4 so e_xk1 should give 1 and 0 when vice versa
and one more thing i would like to mention that i used the if else code at another place without using begin end and it gave correct results....while here i cant avoid using begin end before and after the if else statements....but its leading to wrong ans
Added after 2 minutes:
and yes i intend the output e_xk1 to be a combinatorial one