goatmxj666
Member level 3
Hello,
I designed charge pump circuit which is fully integrated, and I'm doing a post layout simulation with cadence.
my charge pump circuit need clock of 20MHz.
So I designed a clock generator too.
then, I did post layout simulation with the charge pump with ideal clock source (vpulse) and the charge pump with relaxation oscillator that makes 20MHz.
Obviously, the simulation results for the two versions are different.
The results are not completely different, but the oscillator is not as fast as the ideal clock source. (but, the frequency was same.)
Later, when I test the chip, if I use a function generator as a clock source, will the result be similar to the using an oscillator or similar to the ideal clock source?
I designed charge pump circuit which is fully integrated, and I'm doing a post layout simulation with cadence.
my charge pump circuit need clock of 20MHz.
So I designed a clock generator too.
then, I did post layout simulation with the charge pump with ideal clock source (vpulse) and the charge pump with relaxation oscillator that makes 20MHz.
Obviously, the simulation results for the two versions are different.
The results are not completely different, but the oscillator is not as fast as the ideal clock source. (but, the frequency was same.)
Later, when I test the chip, if I use a function generator as a clock source, will the result be similar to the using an oscillator or similar to the ideal clock source?