Is SXCUT layer without label will effect the physical layout and IC functionality?

[nana_7488]

Hi

Hope to find some answer to my problem. I did put SXCUT layer in my layout but didn't label it using SXCUT net. I do have LVS error on soft substrate pin error. I know that SXCUT layer is use to generate isolated substrate region, but not associated with any mask layer, so what happen to my layout if i did put SXCUt layer but didn't label it. Is my layout and design will still working,is it will effect the actual physical design and functionality as I will fabricate my layout.

Thanks in advanced.

Regards

 

[erikl]

SXCUT layer properties and effect should be described in your PDK docu.

 

[nana_7488]

SXCUT layer properties and effect should be described in your PDK docu.

Hi
I've tried to look at the PDK, it only said that SXCUT layer is used to break the substrate region.No other information on the properties or effect, is it only for the tool or effect the actual physical layout. Thanks

 

[erikl]

... is it only for the tool or effect the actual physical layout.

I don't know your process nor your layers' designations.

If SXCUT actually breaks the substrate region, it must have an effect on the physical layout. As I don't know your process, so it could either create a deep isolating N guard ring down to a buried N+ layer (with a new P-well within this isolating N region), or a deep trench etch down through the EPI layer - in order to get something like an SOI isolation.

 

[lamoun]

Hello.
Which is your process?

 

[nana_7488]

Hello.
Which is your process?

Hi, I'm using IBM PDK cmrf8sf. Do you know anything about SXCUT in this?Thanks

 

[lamoun]

Hello,

I thought it would be IBM.
This is an abstract of the IBM's 8RF.

Useful for creating substrate network for simulation and/or enforcing regional placement of devices in LVS

Substrate regions defined by “SXCUT” “drawing”
– Not associated with any mask layer
– Isolates substrate regions for simulation and LVS only

 

[nana_7488]

Hi
Thanks for the info. Just wondering is it still not affect my layout if I do put the SXCUT layer at my subc which connected to bulk of my NFET transistor? I did connected all the subc to the same ground, but is the SXCUT break the region of the substrate it's assume like my layout having different net. Need confirmation, is all my subc still connected together even with SXCUT at the top of it without label, because on LVS it's showed that it's not, but I do understand that SXCUT layer not associated with any mask layer.

Hello,

I thought it would be IBM.
This is an abstract of the IBM's 8RF.

Useful for creating substrate network for simulation and/or enforcing regional placement of devices in LVS

Substrate regions defined by “SXCUT” “drawing”
– Not associated with any mask layer
– Isolates substrate regions for simulation and LVS only

 

[lamoun]

I think that a schematic and the layout of the problem area might help. Also that way I might understand what are you trying to achieve.