Is parallel-if statement in edge trigger block synthesizable?

[iamovid]

Hi guys,
I need ur help. Currently I am working on a project using 2-dimensional arrays.
And for some purposes, I need to implement it in a pipelined way. So I use parallel-if in edge triggered always block.
Related tutorial is referred in this link https://www.asic-world.com/verilog/vbehave2.html.

This is the sample code from ASIC-WORLD.COM
1 module parallel_if();
2
3 reg [3:0] counter;
4 wire clk,reset,enable, up_en, down_en;
5
6 always @ (posedge clk)
7 // If reset is asserted
8 if (reset == 1'b0) begin
9 counter <= 4'b0000;
10 end else begin
11 // If counter is enable and up count is mode
12 if (enable == 1'b1 && up_en == 1'b1) begin
13 counter <= counter + 1'b1;
14 end
15 // If counter is enable and down count is mode
16 if (enable == 1'b1 && down_en == 1'b1) begin
17 counter <= counter - 1'b1;
18 end
19 end
20
21 endmodule


My sample code is as follows

integer i;
reg [7:0] array[0:10];

always@( posedge clk or negedge rstn )
begin
if ( !rstn )
for ( i = 0; i < 10; i = i + 1 )
array <= 0;
else
begin
if ( condition_a )
array[index] <= c;
if ( condition_b )
array[index_delay_1T] <= d;
end
end

in my codes, condition_a and condition_b can be enabled simultaneously which differs from the sample code in ASIC-WORLD.COM

The codes above passed nLint check and seems to be synthesizable using design compiler.

My concern is this a legal way for a design or anything I must take care of it.

Thanks for ur comment in advance.
Apologize for my poor English.