Is necessary I2C to add a reapter for buffering in a divided circuit?

[Enshuo]

Hi,
I study the I2C divides into two nets with a repeater PCA9617ADPJ below (BMC_I2C3_SCL -> BMC_I2C3_OUT_SCL). Every kind of I2C is the same. It looks it's only for buffering (rise/fall time, not voltage shifting). Is it really needed?
Repeater datasheet https://www.nxp.com/docs/en/data-sheet/PCA9617A.pdf

 

[stenzer]

Hi,

is the I²C communication only performed within/on a single PCB? How does the layout/dimensions of this PCB look like with respect to capacitances?
Are there any (long) cables involved to connect e.g. two PCBs?
What is the desired I²C frequency?

So basically, which kind of capacitances are related to your SDA and SCL lines (cables and traces) and at which frequency have those capacitances to be charged and discharged?

BR

 

[FvM]

The noise immunity of an I2C bus becomes not necessarily better by splitting it over multiple partial busses. The main purpose of PCA9617 is level conversion and isolating busses with separately switched power supply. By increasing the output low level to 0.5 V, it might even reduce noise immunity in some cases. Without information about the topology f your bus, it's impossible to decide if the buffer serves a useful pupose.

 

[Enshuo]

Hi,

is the I²C communication only performed within/on a single PCB? How does the layout/dimensions of this PCB look like with respect to capacitances?
Are there any (long) cables involved to connect e.g. two PCBs?
What is the desired I²C frequency?

So basically, which kind of capacitances are related to your SDA and SCL lines (cables and traces) and at which frequency have those capacitances to be charged and discharged?

BR

Hi Stenzer,
Thanks for your reply. All I2C is on a single PCB without cable and connector. The total length is around 21 inches, and the frequency is 1Mhz. It's a good point that is related to capacitances. So, what's the frequency or length that have capacitances generally?

--- Updated Aug 5, 2020 ---

The noise immunity of an I2C bus becomes not necessarily better by splitting it over multiple partial busses. The main purpose of PCA9617 is level conversion and isolating busses with separately switched power supply. By increasing the output low level to 0.5 V, it might even reduce noise immunity in some cases. Without information about the topology f your bus, it's impossible to decide if the buffer serves a useful pupose.

Hi FvM,
Thanks for your reply. The topology is as below. Not sure if it's needed the repeaters to reduce the noise.

 

[stenzer]

Hi,

the trace capacitance depends on the layout by means of trace width and distance to ground plane as well as the chosen layer (Stripline, Microstrip, Embeded Stripline,...). Basically you can estimate this capacitance by considering the trace and the ground plane (underneath) as a parallel plate capacitor. A good tool to determine those kind of capacitances is Saturn PCB Toolkit, it is for free. So your goal is to charge and discharge those capacitances fast enough by choosing appropriate pull-up resistors. See this datasheet P82B715, which addresses the calculation of the pull-up resistors. By assuming a trace capacitance of about 0.5 pF/cm your total trace capacitance would in the range of 25 pF. A typical MCU GPIO pin contributs in an additional capacitance of about 4 pF.

If it comes to noise supression a differntial I²C implementation might be of interest. A possible IC would be the PCA9615.

In my personal point of view the the repeaters are not necessary. Even the pull-up resistors values are already in the range as determined for the mentioned assumptions above. Also the enable pins of the repeaters are not used, which might be of interest if some one has to use the same I²C address multiple times

BTW, what I'm missing are the pull-up resistors on the left side of your repeaters.

 

[Enshuo]

Hi,

the trace capacitance depends on the layout by means of trace width and distance to ground plane as well as the chosen layer (Stripline, Microstrip, Embeded Stripline,...). Basically you can estimate this capacitance by considering the trace and the ground plane (underneath) as a parallel plate capacitor. A good tool to determine those kind of capacitances is Saturn PCB Toolkit, it is for free. So your goal is to charge and discharge those capacitances fast enough by choosing appropriate pull-up resistors. See this datasheet P82B715, which addresses the calculation of the pull-up resistors. By assuming a trace capacitance of about 0.5 pF/cm your total trace capacitance would in the range of 25 pF. A typical MCU GPIO pin contributs in an additional capacitance of about 4 pF.

If it comes to noise supression a differntial I²C implementation might be of interest. A possible IC would be the PCA9615.

In my personal point of view the the repeaters are not necessary. Even the pull-up resistors values are already in the range as determined for the mentioned assumptions above. Also the enable pins of the repeaters are not used, which might be of interest if some one has to use the same I²C address multiple times

BTW, what I'm missing are the pull-up resistors on the left side of your repeaters.

Thanks for your detailed explanation. The repeaters are not enabled indeed, so I thought it's not necessary too.

There are 2.2K pull-up resistors. I didn't attach it. Thanks for mentioning.

 

[FvM]

If the traces are relative long, you'll usually start to reduce the pull-up resistor values, according to the permitted maximum current strength of the connected I2C devices. Next step is reducing the actual buf clock frequency if acceptable for the application. See NXP I2C manual for calculation of pull-up resistors and maximal bus frequency.

The amount of I2C repeaters in the design doesn't seem reasonable at first sight.

 

[Enshuo]

If the traces are relative long, you'll usually start to reduce the pull-up resistor values, according to the permitted maximum current strength of the connected I2C devices. Next step is reducing the actual buf clock frequency if acceptable for the application. See NXP I2C manual for calculation of pull-up resistors and maximal bus frequency.

The amount of I2C repeaters in the design doesn't seem reasonable at first sight.

Totally agree. Should modify the pull-up resistors first after study the **broken link removed**. Besides, there are only two chips (the resistors could cover 400pF). It shouldn't need the repeaters.

 

[stenzer]

The repeaters are not enabled indeed, so I thought it's not necessary too.

The repeaters are enabled as this pin is active HIGH and there is an internal pull-up resistor implemented (see page 3 in the datasheet). By leaving the enable pin floating/unconnected the repeater is always enabled. What I have meant is, there is no possebillity to disable the individual repeaters, which would be neccessery if there are multiple I²C slaves (to the right in your sketch) with the same address.

BR

 

[FvM]

The repeaters are enabled as this pin is active HIGH and there is an internal pull-up resistor implemented (see page 3 in the datasheet). By leaving the enable pin floating/unconnected the repeater is always enabled. What I have meant is, there is no possebillity to disable the individual repeaters, which would be neccessery if there are multiple I²C slaves (to the right in your sketch) with the same address.

Indeed, I don't see an useful purpose of the disable feature in the above sketched topology.