Vamsi Mocherla said:You can write Verilog A code for an ideal DAC and feed the outputs of the ADC to the DAC and then measure the INL and DNL.
Vamsi Mocherla said:For INL and DNL, you really do not need a clock, I mean when you are testing for INL and DNL, you can put the clk to high(or low - depending on your configuration) and run a DC sweep.
Vamsi Mocherla said:Well, you can tie the clock to VDD (or logic one). That should not be a problem. In case, the sampling is a falling edge, tie it to VSS.
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