Is it possible to simulate DNL and INL for a 10-12bit ADC?

[JiL0]

how to inl simulation

Is it possible to simulated DNL and INL for a 10-12bit ADC?

From what i know, to obtain DNL and INL, there is the back-to-back of ADC and DAC method and the histogram method. However, these method are normally for ADCs that are already fabricated and it will take years to do the simulation (or am i wrong?) as we need a lot of sample points.

So, i would like to ask if there is another method to simulate the ADC to obtain its DNL and INL before i send it out for fabrication.

THanks!

 

[codec]

Re: Simulate DNL and INL

For 10~12bit ADC, I think simulation is tolerable.
It is no need to take 10 points per LSB, but 4 is enough to determine whether the DNL and INL is less than 0.5LSB. Such simulation (surely depends on circuit scale) is around 1~3 days if using Linux (CPU 2.8G, RAM 512M).

 

[terryssw]

Re: Simulate DNL and INL

But how we can test the DNL and INL in simulations?

 

[konqueror]

Simulate DNL and INL

please point out a way to simulate dnl and inl for an ADC . i have heard that it is done using the calculator in cadence icfb but can some one point out exactly how it is done

 

[JiL0]

Simulate DNL and INL

Not sure what method codec is refering to but i assume is a ramp test where we see where the transition from 1 bit to another occurs.

For a 12 bit ADC, 4 samples per LSB = 4*4096 = 16 384. Wont that take ages for both a ramp test or a histrogram test?

Maybe my comp is slow as i need roughly 1 hour per sample.

 

[Vamsi Mocherla]

Re: Simulate DNL and INL

You can write Verilog A code for an ideal DAC and feed the outputs of the ADC to the DAC and then measure the INL and DNL.

 

[blue2lucy]

Re: Simulate DNL and INL

You can write Verilog A code for an ideal DAC and feed the outputs of the ADC to the DAC and then measure the INL and DNL.

This should be readily avaiable.

 

[andy2000a]

Simulate DNL and INL

I ever use hspice behavior write a "idea D/A convert" for simulation DNL/INL .. but too idea
and I ever try use add "gitter noise" in clock ..but not work

 

[Vamsi Mocherla]

Re: Simulate DNL and INL

For INL and DNL, you really do not need a clock, I mean when you are testing for INL and DNL, you can put the clk to high(or low - depending on your configuration) and run a DC sweep.

 

[terryssw]

Re: Simulate DNL and INL

For INL and DNL, you really do not need a clock, I mean when you are testing for INL and DNL, you can put the clk to high(or low - depending on your configuration) and run a DC sweep.

?? Without the clock, how can your ADC / DAC works??

 

[wany]

Re: Simulate DNL and INL

I have used ideal DACcell in candance.But Output voltage of my design is from 1.5
to 1.2 .how can i know DNL and INL ?

 

[Vamsi Mocherla]

Re: Simulate DNL and INL

Well, you can tie the clock to VDD (or logic one). That should not be a problem. In case, the sampling is a falling edge, tie it to VSS.

 

[terryssw]

Re: Simulate DNL and INL

Well, you can tie the clock to VDD (or logic one). That should not be a problem. In case, the sampling is a falling edge, tie it to VSS.

I suppose you are going to measure the DNL and INL of the ADC / DAC at transistor level. Many of this type of ADC (e.g. clocked pre-amp and latch in flash, SC-MDAC in pipelined ADC) needs clock to do the normal conversion and generate the code. If you don't apply the clock, how can your ADC work normally??

I don't think it is possible to use DC sweep to find DNL and INL, and you must run some transient analysis.

 

[sergeyr77]

Re: Simulate DNL and INL

You can use mixed mode simulation feature of cadence - imse, I suppose.
So you describe logic part of your ADC by Verilog or VHDL - registers, flip-flops, etc. INL and DNL don't depend upon logic of the design.

 

[andy2000a]

Simulate DNL and INL

have anoyone have spice like "jitter clock source"
for A/D D/A simulation INL DNL

 

[tuza2000]

Simulate DNL and INL

is there any example?

 

[totoro]

Re: Simulate DNL and INL

waiting

 

[pablomilanes]

Simulate DNL and INL

I am needing this information too. There is some documentation or paper available about simulation of A/D converters?

 

[chenliy]

Re: Simulate DNL and INL

I have finished a 10bit 2MHz-sps ADC. I put the output of ADC into the input of DAC. The DAC use Verilog-A language. The logic part of ADC, registers, flip-flops,clock generation etc., use verilog language describing. The simulation uses one day to get INL and DNL (Linux,2.8G CPU,1G RAM).

 

[tuza2000]

Simulate DNL and INL

waiting!!