Is it possible to implement image processing, Spartan-3?

[EDA_hg81]

image processing spartan-3 fpga

I bought XSA-3S1000 from XESS company.
Do you think XSA-3S1000 ( XSA-3S1000 Prototyping Board with 1,000,000 gate Spartan-3 FPGA and 32 MBytes of SDRAM) is possible to implement image processing?

Thank you.

 

[echo47]

Yes, but "image processing" is a broad term. What type of processing do you need? The XC3S1000 is a rather small FPGA, but it still has 24 multipliers and RAM blocks, so you should be able to do some interesting things.

 

[samcheetah]

i have the altium livedesign evaluation kit and it has an XC3S400 FPGA. can i implement a function related to image pre-processing like edge detection, contrast enhancement or image compression? i know that such a small FPGA wont help in computer vision or pattern recognition applications so is it possible to implement something related to image pre-processing.

and there is one other thing. has someone interfaced a CMOS camera to an FPGA?? can somebody show me sample projects?

 

[echo47]

The XC3S400 can do over 2 billion multiply-accumulates per second. That should make it easy to do stuff like contrast enhancement, edge detection, DCT, etc. Xilinx app note XAPP610 describes a DCT in an old XC2S200. I'm not sure what's involved in pattern recognition, but I wouldn't rule it out.

 

[EDA_hg81]

Thank you.

According to an IEEE paper, a H.263 codec was realized by a FPGA with 400.000 gates.

I am wondering how we can decide how many gates do we need for image processing projects?

 

[echo47]

Don't try to translate "gate count" into FPGA size. That's an ancient concept. Modern FPGAs are not gate-level devices. You will get much better results by counting register bits, accumulators, multipliers, memories, and that sort of thing.

Try this Xilinx page. Also click the "Video and Imaging IP" link on the right side:
**broken link removed**

For example, the H.263 encoder+decoder from 4i2i uses a few thousand slices in a Spartan-3. It also uses a few multipliers and quite a few block RAMs:
**broken link removed**
**broken link removed**

 

[samcheetah]

The XC3S400 can do over 2 billion multiply-accumulates per second. That should make it easy to do stuff like contrast enhancement, edge detection, DCT, etc. Xilinx app note XAPP610 describes a DCT in an old XC2S200. I'm not sure what's involved in pattern recognition, but I wouldn't rule it out.

over 2 billion MACs!!!!!!!!!!

if im not mistaken, only the DaVinci DSPs from TI can perform upto these levels. where did you get this figure from?

 

[EDA_hg81]

thanks

 

[echo47]

The XC3S400-4 has 16 multipliers. Each one can go about 150 MHz (faster if you are careful). Next to each multiplier is a convenient dual-port Block RAM (for storing data and coefficients) and logic fabric for building accumulators, pipelines, sequencers, and other stuff. 16 times 150 MHz is 2.4 billion MACs. That's not bad for a little chip that costs only $20 US in small quantity.

Now imagine what you could do with a larger Spartan-3 or Virtex familiy device. I've done 20 billion MACs in a big old Virtex-II chip. A modern Virtex-4 SX would be another five or ten times faster.