Is it possible to have Aspect ratio of less than 1 in analog circuit design i.e. W<L

[shrikant_joshi7]

Is it possible to have Aspect ratio of less than 1 in analog circuit design i.e. W<L

I am designing gain boosted Operational amplifier in Cadence which has gain of 76dB but the W/L ratios of many transistors are <1,is it allowed to have W<L?

 

[erikl]

... is it allowed to have W<L?

Of course! But there's also a process dependent W_min.

 

[shrikant_joshi7]

yes,the minimum value of W is 120nm and L=100nm for 90nm technology in Cadence gpdk90.I m using 120nm width and 800nm length for some transistors.Is it appropriate to use this much high value of length.

 

[erikl]

I m using 120nm width and 800nm length for some transistors.Is it appropriate to use this much high value of length.

Yes, totally ok! Some simulation models would warn you if you'd use a too large (or too small) aspect ratio, because the sim. model then wouldn't be accurate enough, but this usually applies to (both) 20:1 ≦ W:L ≦ 1:20 .

 

[shrikant_joshi7]

Is it necessary to take the values of width and length to be a multiple of default minimum value.e.g default W=120nm and length=100nm for gpdk90,then can we take the width of a MOS equal to 140nm or it should be either 120/240/360.......

 

[erikl]

Is it necessary to take the values of width and length to be a multiple of default minimum value

No, not necessary -- you can take any value^*) above.

^*) The granularity of the layout grid sets a lower limit to resolution.