Is it okay to use a counter as a pll integer N divier?

[zhangljz]

Is it okey to use a counter as a pll integer N divier ?

Hello,

I am designing a PLL with low output frequency (~350MHz, reference frequency: 10MHz). I want to have a divider ratio from 1 ~ 63.

Because the frequency is low, and divider ratio is not very high, is it ok to just use a synchronous counter synthesized by verilog to work as a divider, instead of using swallow method. Also I am not familiar with the swallow counter.

Any advice?

Thank you

 

[vfone]

Re: Is it okey to use a counter as a pll integer N divier ?

You can use an offset PLL.

**broken link removed**

 

[biff44]

Re: Is it okey to use a counter as a pll integer N divier ?

yes you can make a programmable synchronous (or non synchronous) counter. if you are doing one with software instead of actual gates....you can have varying time delays in the division, which would give rise to time jitter (phase noise) so you must be careful.