[SOLVED] is it fine to ECO's at placement stage to fix setup violations ? if not where we use?

[n.suresh60]

i have 100 setup violations after placement, how would i fix , can i write eco's at this stage?
please explain me..

 

[artmalik]

At every stage the fixing can be done ....but it makes sense to postroute stage to be used for final fixing of the setup times

 

[layowblue]

It depends on whether the chip is gonna tapeout soon or not.
If time is permitted to do another synthesis/P&R round, fixing RTL is the best way.
If not, and if it is within the range of layout tuning capability, you still have other choice:
- Switch cell from possible hvt to svt/lvt (depends on how much slack the violation indicates)
- tune clock tree along these pathes
If not, there is no other way than ECO the layout netlist. Theoretically, you can fix anything digital with ECO. However, ECO process could be elongated, and iterative, especially if these 100 violations are of different type of issues. Be prepared that LEC would fail and you would have to do another round of ECO tuning.

i have 100 setup violations after placement, how would i fix , can i write eco's at this stage?
please explain me..

 

[n.suresh60]

Hi friends..
@layowblue and @artmalik thank you very much for your response and you cleared my doubts about eco's use.

 

[rca]

when you indicate violations after placement, the post placement setup optimisation is done?

 

[n.suresh60]

hi ..
yes i have seen after postplacement optimization.