Jan 8, 2008 #1 V vsmGuy Advanced Member level 2 Joined Jun 26, 2006 Messages 503 Helped 44 Reputation 88 Reaction score 15 Trophy points 1,298 Location VddVss Activity points 3,882 Mixing logic families Guys, Is it advisable to interface LS family digital logic parts with a uC like AT89C52 or PIC, or should I use HC parts instead ? For example, would it be a good idea to connect a 74LS74 to the above mentioned uC pins or would it be better to connect a 74HC74 ? An anecdotes and ideas/suggestions ?
Mixing logic families Guys, Is it advisable to interface LS family digital logic parts with a uC like AT89C52 or PIC, or should I use HC parts instead ? For example, would it be a good idea to connect a 74LS74 to the above mentioned uC pins or would it be better to connect a 74HC74 ? An anecdotes and ideas/suggestions ?
Jan 9, 2008 #2 E ehsanelahimirza Full Member level 6 Joined Feb 24, 2006 Messages 334 Helped 28 Reputation 56 Reaction score 7 Trophy points 1,298 Activity points 3,570 Mixing logic families there is no problem at all using LS and in both cases some times u need to use buffer ICs like 74245 again 74LS245 mostly used
Mixing logic families there is no problem at all using LS and in both cases some times u need to use buffer ICs like 74245 again 74LS245 mostly used
Jan 9, 2008 #3 V vsmGuy Advanced Member level 2 Joined Jun 26, 2006 Messages 503 Helped 44 Reputation 88 Reaction score 15 Trophy points 1,298 Location VddVss Activity points 3,882 Mixing logic families The ATMEL 89 series and PIC seem to have TTL compatible IO. Hence, LS should not be a problem. I was sorry I did not mention this, because I had a mind block with the clock freq. What I was querying about was whether anyone had speed sync issues. LS logic hit the max at ~25Mhz whereas HC at ~65Mhz, unless I am mistaken.
Mixing logic families The ATMEL 89 series and PIC seem to have TTL compatible IO. Hence, LS should not be a problem. I was sorry I did not mention this, because I had a mind block with the clock freq. What I was querying about was whether anyone had speed sync issues. LS logic hit the max at ~25Mhz whereas HC at ~65Mhz, unless I am mistaken.
Jan 9, 2008 #4 E ehsanelahimirza Full Member level 6 Joined Feb 24, 2006 Messages 334 Helped 28 Reputation 56 Reaction score 7 Trophy points 1,298 Activity points 3,570 Mixing logic families it may create problem if we use high freq signal but we cant use even 20 MHz in case of 8951 8952. i think you can now easily get my point
Mixing logic families it may create problem if we use high freq signal but we cant use even 20 MHz in case of 8951 8952. i think you can now easily get my point
Jan 10, 2008 #5 V vsmGuy Advanced Member level 2 Joined Jun 26, 2006 Messages 503 Helped 44 Reputation 88 Reaction score 15 Trophy points 1,298 Location VddVss Activity points 3,882 Mixing logic families Yes, indeed. You have a very important point there. For such slow speed uC, we don't need high speed glue. Do we ? I don't think so. Unless we are making hardware to slow down a faster device to interface with the slower uC.
Mixing logic families Yes, indeed. You have a very important point there. For such slow speed uC, we don't need high speed glue. Do we ? I don't think so. Unless we are making hardware to slow down a faster device to interface with the slower uC.