Is is able to change STIW in any tools and observe different simulations results?

[Alex Liao]

I am using cadence virtuoso to conduct experiments about STI's (shadow trench isolation) effects. I noticed there is a STIW (width of STI) that could results in mobility changes from this paper " Exploiting STI Stress for performance" Andrew B. Kahng et. al.

I am wondering about
1. at which stage STIW is planed? in layout stage?
2. at which stage STI is really formed/ trenched?
3. by using which kit I can change the STIW (customize it) and most important of all, observe the consequence (e.g. simulate a circuit and see the performance of post-layout simulation) brought by doing so?

Thank you!

 

[dick_freebird]

As a rule the foundry will assert a single trench width in
order that they can optimize the process. This especially
true when STI bottoms to a buried oxide and depth is
then critical.

Then they will characterize strain effects at that single
feature size. Although, if you could drill into the process
development history, you might find device data across
whatever DoXs they did in the course of picking that number.

A good TCAD process-simulator tool might be able to figure
stresses / strains, and pass that to a device simulator as
the meshed structure, but I suspect this is not universal
capability, perhaps rare. I doubt very much that you will
find a PDK that allows, let alone faithfully models at the
circuit simulator level, variable STI width. They have enough
trouble fitting single STI width strain effects against variable
drawn FET width; don't see how allowing that degree of
freedom holds any upside for them.

Back when I worked deeper-trench process developments
we didn't even allow the choice to merge vs run double at
spacing; that alone was too much variation in device
performance and lithographic consistency, to tolerate.
We just built the standard trench into the PCells and
required a minimum trench-trench spacing. We had enough
trouble with trench integrity (deep SOI) that belt and
suspenders seemed like a good idea. Double insulated,
device to device, as it were.

 

[Alex Liao]

Hi dick_freebird,

Thank you. You must be born with English as mother language. With your response, I did a lot of discussion with my supervisor. Sometimes what you said may not fully communicate to us. But definitely your experience is largely helpful in this thread. Therefore, I want to double check with certain sentences. Hope you can clarify that.

As a rule the foundry will assert a single trench width in
order that they can optimize the process.

If the space, between two active area, where STIW needs to be placed/formed is 10um, is the foundry able to place a 10um wide trench directly or place 10 * 1um STIW to make it looks like a 10um wide trench assuming 1um is what you have talked about "assert a single trench width" as a constant or fixed feature.

I doubt very much that you will find a PDK that allows, let alone faithfully models at the circuit simulator level, variable STI width.

This means, the effects of STI width cannot be verified at circuit simulator level.

don't see how allowing that degree of freedom holds any upside for them.

I really do not know what does "holds any upside for them" mean. Poor me. :-(

We just built the standard trench into the PCells and
required a minimum trench-trench spacing.

By saying so, again, it seems you places multiple trenches and forms into a wider isolation space. PCells means we can do something in PDK, the circuit simulator level, isn't it?

If both of us believe STIW can have some effects on performance or whatever, there must be ways of varying it. (e.g. 100nm STIW exerts much stain stress on both side and thus deteriorate the mobility as well as the whole performance comparing to a 10um STIW which is costly for sure.) Is there any hope to see it only at circuit simulator stage or even TCAD stage? Any suggestions on at least in which stage the STI width variation & verification is enabled?:wink:

I can only speak those normal English. Sorry for any trouble on your side.

Alex

 

[dick_freebird]

(1) The trench needs to isolate the individual device, it
does not need to fill all of the space between devices.
There can be clear field with the trench only bounding
the edges where it abuts active devices.

(2) STI effects at the simulator level depend upon some
parameterization (and this, based on fitting - in turn based
on some substantial variations all being tested) in the
model. I have only seen intradevice strain effects attempted,
nothing for the trench width outside active area (although
indeed this does matter). The foundry is more interested
in consistency and keeping modeling effort to a minimum,
than enabling experimentation in a second- or third-order
layout effect.

It's not that it can't be done, it's that

(3) "upside" means some value for them, in making a mask
feature variable instead of fixed. The "downside" is more to
control, more complaints from users who took the geometry
away from normal and toward the design rule limit, more
work in characterizing a span where a single value would
suffice. This would be done in early process development,
a best-capability target found, and then that feature
"locked" - the variations should have been done for your
benefit already, you just don't get to see this, and any
excursion from the standard ought to be worse in some
way or other (presuming diligence on the foundry's part).

(4) You could fill with dummy trenches of compliant width
and space, but these would be only isolating nothing from
nothing (but, perhaps making more uniform lithographic
loading, etc.). If there is a maximum trench-trench space,
or rules for "dummy islands" / density, then filling with
some unit-trench features may be needed for rules
compliance. I doubt there is any electrical value though.

I suspect that some TCAD tools may let you model the
trench stress/strain on the device-region silicon and
the electrical outcomes, but also suspect this is a long
iterative research-y path. I would not expect first-pass,
first-principles success here; many nuances besides the
trench geometry at play (trench fill, thermal process
inputs, trench oxide interface qualities, ...).

 

[dick_freebird]

Here is a TCAD tool that addresses your interest at the physical
level.

**broken link removed**

 

[Alex Liao]

I'll try to figure out those new information from you.

Thank you so much