you have the full optionality in this case.
you can make a seperate module as MY_RAM and define its behavior and access to its ports just like an external ram.
or u can define ram inside your design very simply. for example for a dual port BRAM we have:
process (<clock>)
begin
if (<clock>'event and <clock> = '1') then
if (<enableA> = '1') then
if (<write_enableA> = '1') then
<ram_name>(conv_integer(<addressA>)) <= <input_dataA>;
end if;
<ram_outputA> <= <ram_name>(conv_integer(<addressA>));
<ram_outputB> <= <ram_name>(conv_integer(<addressB>));
end if;
end if;
end process;
from this moment on, if u wanted to read smthing from specified address, you must adjust "addressA" with intrested adresa and then put '1' in "enableA" signal. the requested data is ready on "ram_outputA" on next clock edge. and if you want to write somthing provide the addreassA and input_dataA with intrested data and then put '1' on the "write_enableA" signal....