Not a Verilog expert but seems to me you need to count clock edges and
then decode the state of that 2 bit divide by 3 cntr ? And that state used
to invoke the task needed for that N'th clock edge.
Code:
module 2_bit_Count(
input clock, reset,
output [1:0]dout
);
reg [1:0]dout;
initial dout = 0;
always @ (posedge (clock))
begin
if (reset)
dout <= 0;
else
dout <= dout + 1;
end
endmodule
Just add the state reset on 3 and the needed if statements to test count state
for task trigger.
Regards, Dana.