Hi friends,
I want to implement an asynchronous FIFO myself in VHDL, but I do not know how to generate the empty and full flag in that I don't know how to compare the write pointer with the read pointer with different clock domain.
I heard that using gray code could meet the command,but How?
Welcome anybody familiar with it to discuss with me about it!
arena_yang you can also learn a lot looking
at how people at http://www.free-ip.com/ramlib/fifo.html
implemented async fifos in vhdl. You can
download full source code there !
Greets