Is anybody doing prjt in fft implemented using verilog/vhdl

[shijinasyed3]

My project title is "PIPELINED PARALLEL FFT ARCHITECTURES VIA FOLDING TRANSFORMATION"....

IS anybody having verilog codings related to RADIX 2 MULTIPATH DELAY COMMUTATOR?

IF POSSIBLE PLS SEND CODINGS FOR RADIX 2 8 POINT DIF FFT WITH ITS CORRESPONDING DIAGRAM............