shivakumay.gy
Newbie level 6
FPGA
process(s1,clkk)
begin
if rising_edge(clkk) then
ssout1<='1';
ssout2<='1';
ssout3<='1';
case s1 is
when "0000000" => ssout1<='0' after 8 ms;
in this highlighted line can be implemented in hardware are not. and is it synthsizable or not. please any body can help me for this..................
reply for me to this mail shiva.yaragal@gmail.com[/u][/i]
process(s1,clkk)
begin
if rising_edge(clkk) then
ssout1<='1';
ssout2<='1';
ssout3<='1';
case s1 is
when "0000000" => ssout1<='0' after 8 ms;
in this highlighted line can be implemented in hardware are not. and is it synthsizable or not. please any body can help me for this..................
reply for me to this mail shiva.yaragal@gmail.com[/u][/i]