Is ADPLL's jitter related to the frequency of PLL?

[bracketx]

If the control of ADPLL is according to the counter, low frequency means a bad jitter. Is that true?

 

[rfsystem]

Did you mean low comparison frequency? If the frequency control is digital there is no difference to a time discrete value continiuous control. The problems are in the detail:

1. Digital control with high resolution is often nonmonotonic or has to use multiple segments.

2. Phase resolution requires to count at very high frequencies. In a analog PLL you get some ps resolution (noise limit)

Try to calculate the noise performance of your complete digital ADPLL. Then you know how many bits you need there.

 

[bracketx]

what's the multiple segments?Do you mean that ADPLL is not suitable for low time jitter PLL design?