procedure cgen(signal clk : out std_logic; constant FREQ : real) is
constant P: time := 1 sec / FREQ;
constant HIGH_T : time := P/ 2;
constant LOW_T : time := P- HIGH_T;
begin
loop
clk <= '1';
wait for HIGH_T;
clk <= '0';
wait for LOW_T;
end loop;
end procedure;
2. It's not clear if and why you need the 73 MHz frequency to be exact, and which error would be acceptable. The only understandable reason I can imagine is that you want to implement a certain clock frequency ratio
What are you simulating that needs such a precise clock in simulation?
I do need it for communicating with a custom asic that runs at 73Mhz that do encryption.
So what is the syntex for running 73Mhz on simulation?
Have you ever done timing simulation?It's simulation. Clock frequency doesn't matter. It's all virtual.
Have you ever done timing simulation?
Have you ever done timing simulation?
I do need it for communicating with a custom asic that runs at 73Mhz that do encryption.
So what is the syntex for running 73Mhz on simulation?
Correct,The OP just wants to generate a 73MHz signal as accurately as possible with 50% DC. He will use it for simulation. Thats it I think.
Does this make sense?I'm doing timing simulation,
to those who asked, my acurrcy is 3 digits after the dot.
Defective pocket calculator?1/73MHZ = 1.369 ns period
YesDefective pocket calculator?
So what is the syntex for running 73Mhz on simulation?
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