IP core FIFO without free-running clock

[todonu]

Hi,

I need two send data syncronously thru two clock domains.
- One of them ( the read which is outside the FPGA) is a interface that does NOT have a free running clock.This interface (GPMC) generates the read clock.
- The other (Write which is inside the FPGA) has a free running clock - the write clock.

I was considering the use of a dual port FIFO IP core but it seems that xilinx FIFO design demands free running clocks.

Can anyone suggest me a way to do this? Do I need to design another FIFO with clock domain synchonizers!!

Thanks a lot for any comments

 

[FvM]

You specifications about the interface are too vague. What makes you think that you need a FIFO at all?

 

[todonu]

thks,

I have huge amount of data(bus 16 bits) available in the FPGA that I want to read using the GPMC interface of an ARM processor. Reading synchronously.
Since I have two clock domains (different frq and phase) I thought of using xilinx IP CORE dual port FIFO. I have setup everything to avoid fifo overflow and ... so .on...
My problem is not FIFO ... My problem is that if the RD_CK is not free running and the xilinx FIFO is not granted to work.
RD_CK is the GPMC CK which is turned ON (By the ARM processor) ONLY during READ transfer.

I am also evaluating possibilities and I do not know if using one BUFGMUX to MUX the clocks (RD_CK with the FPGA CK = WR_CK) can be a solution...

 

[FvM]

The read operation of a processor is expecting an immediate answer, in so far a FIFO won't help much. The ususal method is by synchronizing the asynchronous processor control signals (RD, WR, CS) to the other clock domain and process it therein. At the ARM side, wait states have to be added in the bus setup of the respective peripheral address range.