[SOLVED] IO-Pin/Pad voltage of a flash based FPGA

[dpaul]

Hello,

I am working on a flash based FPGA project and I received a question from the PCB engineer which kept me wondering.

"Is there a problem if an unused pad of 3V3 IO/Bank is connected to 1V2 voltage? "

Background:
-- In this project 1.2V is the Core Voltage
-- Default IO Technology has been set to LVCMOS 3.3V

Keeping aside the need to do such a thing and assuming that the above needs to be implemented,
will it make sense that I use the IO Editor tool and change the setting only for that particular pin to LVCMOS 1.2V?

 

[FvM]

Which FPGA family? I don't expect that voltage class can be edited for a single IO pin, usually it's applied bank wise. Input threshold ist typically set by the actual bank VCCIO, not editor settings.

What's the pin function? If you say it's unused, does it actually require Vih level, can't it be set to GND or to high by an internal weak pull-up?

 

[KlausST]

Hi,

I/O pin voltage has nothing to do with core supply voltage.

So we need to refer to the bank supply voltage (and maybe the internal pin settings)
In my opinion (without knowing details about your FPGA and so on)
1.2V is a bad idea for a 3.3V supplied I/O. It may cause increased power supply due to crowbar current wihtin the input stage.

General recommendation: Pull as close as possible to the supply rails.
Externally using a resistor or internally as OUTPUT or INPUT_WITH_PULLUP/DOWN.
Maybe your FPGA provides a buskeeper feature.

Klaus

 

[dpaul]

@FvM,
It is the Igloo-Nano FPGA.

Which FPGA family? I don't expect that voltage class can be edited for a single IO pin, usually it's applied bank wise. Input threshold ist typically set by the actual bank VCCIO, not editor settings.

What's the pin function? If you say it's unused, does it actually require Vih level, can't it be set to GND or to high by an internal weak pull-up?

From my Xilinx background, I also had the idea as marked in BOLD above.

As mentioned, it is an unused/unconnected pin. A pin constrain for it does not exist within the PDC file.

However see the Libero Project settings as shown below. By the term "......change individual I/O attributes" I thought I can change for individual pins. May be I am wrong, and the tool will allow me to change many other attributes but not the voltage. I am yet to go deep inside Libero and try.

--- Updated Oct 28, 2022 ---

I/O pin voltage has nothing to do with core supply voltage.

Yes I know that.
Perceive it as, "an unused FPGA pin, which has a bank voltage of 3.3V is connected to 1.2 Volts."

 

[FvM]

The FPGA family provides configurable pull-up/-down resistors for all IO pins and doesn't need to connect unused pins. I don't remember the Libero features, but I expect a default setting for unused pins.

 

[ads-ee]

The "Please use the I/O Editor to change individual I/O attributes" means that you should use the I/O Editor for editing things like the pullup/pulldown, input hysteresis, input delay, etc attributes for each (individual) pin.

The I/O voltage levels are set by the bank voltage and setting them to something other than a acceptable I/O standard for that bank voltage will result in a failure during place and route in designer.

I also agree with KlausST if the actual level of that unused pin is 1.2V then it will likely cause a issue with current through the input buffer of that pin. Microchip parts default to a weak pullup to ensure the input buffers don't have unnecessary current draw if they are left unconnected.

 

[KlausST]

Hi,

Background:
-- In this project 1.2V is the Core Voltage

I just referred to your given information. I don´t know why you posted this information, if you already knew it has nothing to do with your problem.

Klaus