Hi All,
In my design I need to shift a 0.4V signal clock to a 1.2V signal clock, the clock is a ring osc with a 0v4 supply.
I implemented two inverters in cascade as level shifters, with the first stage inverter having an HVT pmos and an LVT nmos, while the second stage are just normal pmos and nmos. It seems to work and copies the clock signal with just a higher level.
I would just like to ask, what problems could this have over the typical latched level shifter? It seems to work fine, but I am not very familiar with level shifters.