inverter circuit design

[archusvijay1]

Hi,
i want to design an inverter with two dc source which has an output of sinusoidal AC.The circuit diagram is not working properly which i attached here.any body please tell how it work properly already i spend lot of time for this project.

my doubts are
1. whether the mosfet driver used for H Bridge in this is correct or not?. Is the same mosfet driver is used for the other two switches ? if not which mosfet driver is used?
2.with the gate open i had given dc supply to the connector J2, it showing a short circuit ,why it is like that?


please help......

 

[KlausST]

Hi,

I recommend to spend some time to study literature on how inverters, H bridges, FETs and the other electronic work.

No engineer would leave gates open while powering mosfets.


Klaus

 

[Venkadesh_M]

with the gate open i had given dc supply to the connector J2, it showing a short circuit ,why it is like that?

Because you just damaged them.

Yeah you better start electronics after a good basics, but here is the reason if you let your mosfet gate open it can easily turn ON and can short Vcc and Gnd with another MOSFET in the same limp of H bridge.

When there is no signal input they should short circuited or terminated with a parallel resistor. In your circit you are having a 10 k in gate. Just put it in the same board of MOSFET.

 

[archusvijay1]

hi,
I think you people had misunderstood me. actually i want to implement a five level inverter with new pwm technique.it is already simulated in matlab and we got the output.we had also implemented the program part in dsp processor .now we are doing the hardware part.i have little knowledge in the hardware section,so i have some problem to implementing the hardware.

when i referred more i had gone through some modification and tried to implement it but again failed.the modified circuit is attached with this.please any one tell the problem in the circuit diagram.

 

[rudr_p]

I think that is happening because your schematic is wrong, for a 5 level h bridge there are 2 isolated dc supply and 2 separate h-bridges which I don't see. Since you powering up from j2 then the 2 mosfet those below h bridge one is conduction by the internal diode assuming at 'com ' is neutral point. I don't under the purpose of those two mosfet below.

 

[Venkadesh_M]

what i understood from the schematic is you are trying to have

inverter voltage V = V1 + V2 if M6 ON and M5 OFF
V = V1 when M6 OFF and M5 ON.

for that you have to interchange M6 and J2 otherwise M6 should be P-channel device because the current is in opposite direction also choose the MOSFETs having no free wheeling diode for this purpose.

you should keep at least one of the M5 and M6 transistor OFF otherwise it will cause short circuit the V2.

What is the PWM frequency ? what is the speed of MCT2 ?

There is mistake in voltage of VDD and VCC pins of IR2110 they have been interchanged.

What is the voltage of V1 and V2 ?

 

[KlausST]

Hi,

... as said pwm frequecncy is important to know...

Are you sure that driving the bootstrap circuit with 5V is ok?

Are you sure that the output circuit (3× R, x C) is good for driving FETs? Especially the 100R series resistor and the 1k parallel to gate is unusual.

I also can't find how this is a 5 level system.
Usually there should be a capacitor at the high side fet source.

Klaus

 

[Venkadesh_M]

Are you sure that driving the bootstrap circuit with 5V is ok?

As I have already pointed out voltages 5 and 12 are wrongly placed, they have to be interchanged.

Are you sure that the output circuit (3× R, x C) is good for driving FETs? Especially the 100R series resistor and the 1k parallel to gate is unusual.

I think the schmatic in design phase and the 100ohm and 1k can be replaced with 10ohm and 10k resistors. I just used the old schematic which doesnt have them.

I also can't find how this is a 5 level system.
Usually there should be a capacitor at the high side fet source.

I think the bootstrap cap C7 value can be changed enough as usual value of 22uF. but it is also depend of PWM frequency.

 

[archusvijay1]

As I have already pointed out voltages 5 and 12 are wrongly placed, they have to be interchanged.

i already interchanged this mistake.

[I think the schmatic in design phase and the 100ohm and 1k can be replaced with 10ohm and 10k resistors. I just used the old schematic which doesnt have them.]

In the schematic i had marked wrongly but in hardware i put 10 ohm and 10k resistors

[I think the bootstrap cap C7 value can be changed enough as usual value of 22uF. but it is also depend of PWM frequency.

The width of some of the signals are in milli range and some have micro range,so i chose the capacitor value as 0.47uF. Is any error in this value?

[for that you have to interchange M6 and J2 otherwise M6 should be P-channel device because the current is in opposite direction also choose the MOSFETs having no free wheeling diode for this purpose]

As you said i had used M6 during simulation. but it is impossible in the case of hardware because of free wheeling diode.can i use IGBT instead of mosfet, or is there any mosfet without any free wheeling diode?

 

[KlausST]

Hi,

i chose the capacitor value as 0.47uF. Is any error in this value?

you keep PWM frequency as a secret...
...but maybe you can tell us what absolute maximum ON time of the high side FETs is? Then we can say if it is enough or not.

(I usually use 100nF, and never had any problems with it, but i have a completely different design. No R parallell to gate, max 99% duty cycle by design, low impedance bootstrap path...)

Klaus

 

[Venkadesh_M]

There are lot of modifications needed in the circuit. Is your gnd and com connected ? Also make sure V1 and V2 are totally isolated sources neither ground.

 

[archusvijay1]

you keep PWM frequency as a secret.....
...but maybe you can tell us what absolute maximum ON time of the high side FETs is? Then we can say if it is enough or not.

Klaus

Hi Klaus,
i can,t say any particular frequency because here add two or more pwm signals to generate a single pwm pulse to the switches.

maximum ON time is around 2mS and minimum on time is around 0.02uS.

I usually use 100nF, and never had any problems with it, but i have a completely different design. No R parallell to gate, max 99% duty cycle by design, low impedance bootstrap path...

i will try with 100nF capacitor. can you tell about low impedance bootstrap path?

- - - Updated - - -

Hi,

There are lot of modifications needed in the circuit. Is your gnd and com connected ? Also make sure V1 and V2 are totally isolated sources neither ground.

Gnd and Com are not connected together.I think the Com Potential is not zero voltage. i use V1 and V2 are two separate sources.

 

[Venkadesh_M]

Gnd and Com are not connected together.I think the Com Potential is not zero voltage. i use V1 and V2 are two separate sources.

But you need to connect com and gnd for H bridge.

 

[KlausST]

Hi,

i will try with 100nF capacitor. can you tell about low impedance bootstrap path?

bootstrap capacitor size:
if you need at least 10.5V (just an example voltage) at bootstrap capacitor to operate properly and have 12V supply voltage then:
The capacitor is dischrged by
1) the ammount of gate charge you need to switch on the FET
2) leakage current in all traces, capacitor and circuitry around the bootstrap and FET gate multiplied with time
3) resistor paralleled to FET gate currrent multiplied with time.
solution:
1) read the datasheet of the FET
2) i´d estimate it with less than 10uA ( x 2ms)
3) i = U / R = 11V / 10k = 1mA ( x 2 ms = 2uAs)

The biggest part will be 3).
Capacitor calculation: voltage drop = 11.5V -10.5V = 1V, current = 1mA, time = 2ms
C = I * t / U = 1mA * 2ms / 1V = 2uF

==> so with your circuit the 470nF is not enough. Go for a capacitor bigger than 2uF. I reccomend >= 4.7uF X7R ceramics.

******

Low impedance path:
Short wide traces, highspeed diode, ceramics bootstrap capacitor. and a ceramics capacitor at the supply voltage near the bootstrap diode.
All this ensures that the bootstrap capacitor charges within a short low time.

 

[archusvijay1]

thank you all for your valuable suggestions
i will try these things and come back again

 

[archusvijay1]

Hi,
with your help i was able to complete my work successfully. thank for your support.
There have some distortion in the output how can i reduce it?
Is it due to the problem in PCB?