Hi
I am a PD engineer with ~10 yrs experience working in a product based company
I am looking to move to some of the new entries to semicon job market (Google/Amazon etc)
Of course , with 10 yrs exp, I have acquired some skill set wrt to Timing closure, Partitioning, PnR etc and worked on about 10 tape outs
However , in the interview process I am falling short.
To elaborate a little more I have worked on backend end implementation for different IPs/SOC blocks but mainly I have worked on block level PnR
Unfortunately , since in most of the companies I have worked in there was a strong backend CAD flow, I have limited (basic knowledge) exposure to constraints , clock architecture & proper understanding of design specific STA challenges, impact of DFT architecture on STA
Also the signoff was handled by respective signoff teams
Would really appreciate if some experienced folks from any domain (PD/STA/DFT even frontend) could help with some interview tips for 10 + yrs job openings and suggest on how to improve my knowledge .
I am also looking for some training in advanced STA concepts (like IP specific STA challenges) to help fill the gap..any leads would be appreciated.