Feb 27, 2011 #1 S spartanthewarrior Full Member level 2 Joined Jun 13, 2007 Messages 122 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,296 Activity points 2,142 Hi All, Can anybody help me answering a question. Note:- Don't as Jitter, Set-Up, Hold Time Values. I need Verilog logic. How can i find a duration of a given (Clock) using Verilog. There are two cases when 1) Duty Cycle is 50% 2) Duty Cycle is 30% Please help me it's important
Hi All, Can anybody help me answering a question. Note:- Don't as Jitter, Set-Up, Hold Time Values. I need Verilog logic. How can i find a duration of a given (Clock) using Verilog. There are two cases when 1) Duty Cycle is 50% 2) Duty Cycle is 30% Please help me it's important
Feb 27, 2011 #2 L lostinxlation Advanced Member level 2 Joined Aug 19, 2010 Messages 699 Helped 197 Reputation 394 Reaction score 183 Trophy points 1,323 Location San Jose area Activity points 5,051 If you try it and show some effort, we'll help you.
Feb 28, 2011 #3 E ebuddy Full Member level 3 Joined May 15, 2007 Messages 177 Helped 35 Reputation 70 Reaction score 34 Trophy points 1,308 Activity points 2,372 It should look something like this: initial begin #500; // wait clock to be stable @(posedge clk) t1 = $time; @(posedge clk) t2 = $time; $write ("The period is : %t", t2-t1); end
It should look something like this: initial begin #500; // wait clock to be stable @(posedge clk) t1 = $time; @(posedge clk) t2 = $time; $write ("The period is : %t", t2-t1); end