#pragma config PLLDIV = 5 // 20 MHz external clock / PLL prescaler value of 5 = 4 MHz required input to PLL circuit
#pragma config CPUDIV = OSC1_PLL2 // non-PLL postscale / 1 OR PLL postscale / 2 for CPU clock speed, depending on FOSC setting below
#pragma config USBDIV = 2 // USB clock source = 96 MHz PLL source / 2, (full-speed USB mode)
// if desired, could change this line to "FOSC = HS" & "oscillator postscaler" gate would be used
// (not the "PLL postscaler" gate), CPU speed would be 20MHz, USB circuitry would still receive 48Mhz clock
#pragma config FOSC = HSPLL_HS // use high-speed external osc crystal, & use PLL postscaler gate to feed CPU (CPU speed = 48 MHz)