hello,
on a 16F1847 , **broken link removed**
6.0 REFERENCE CLOCK MODULE
The reference clock module is controlled by the
CLKRCON register (Register 6-1) and is enabled when
setting the CLKREN bit. To output the divided clock
signal to the CLKR port pin, the CLKROE bit must be
set. The CLKRDIV<2:0> bits enable the selection of
eight different clock divider options. The
CLKRDC<1:0> bits can be used to modify the duty
cycle of the output clock(1). The CLKRSLR bit controls
slew rate limiting.
so, you can have 8 different FOSC values on Pin RA6, independantly of FOSC used for MCU
so i think some PIC24 must have this option ...