WARNING:Xst:2042 - Unit bidir: 8 internal tristates are replaced by logic (pull-up yes): bidir<0>, bidir<1>, bidir<2>, bidir<3>, bidir<4>, bidir<5>, bidir<6>, bidir<7>.
INFO:Xst:2261 - The FF/Latch <t2/b_0> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/b_0>
INFO:Xst:2261 - The FF/Latch <t2/b_1> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/b_1>
INFO:Xst:2261 - The FF/Latch <t2/b_2> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/b_2>
INFO:Xst:2261 - The FF/Latch <t2/b_3> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/b_3>
INFO:Xst:2261 - The FF/Latch <t2/b_4> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/b_4>
INFO:Xst:2261 - The FF/Latch <t2/b_5> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/b_5>
INFO:Xst:2261 - The FF/Latch <t2/b_6> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/b_6>
INFO:Xst:2261 - The FF/Latch <t2/b_7> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/b_7>
INFO:Xst:2261 - The FF/Latch <t2/outp_0> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/outp_0>
INFO:Xst:2261 - The FF/Latch <t2/outp_1> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/outp_1>
INFO:Xst:2261 - The FF/Latch <t2/outp_2> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/outp_2>
INFO:Xst:2261 - The FF/Latch <t2/outp_3> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/outp_3>
INFO:Xst:2261 - The FF/Latch <t2/outp_4> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/outp_4>
INFO:Xst:2261 - The FF/Latch <t2/outp_5> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/outp_5>
INFO:Xst:2261 - The FF/Latch <t2/outp_6> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/outp_6>
INFO:Xst:2261 - The FF/Latch <t2/outp_7> in Unit <Top> is equivalent to the following FF/Latch, which will be removed : <t1/outp_7>
Hi,,
I synthesised my implementation of a bidirectional bus after unselectingthe
ADD IO BUFFERS option in the synthesis menu of the Xilinx IST . My device is Virtex 4 and I got the above message. What exactly does this mean ? and how may the pull up data affect my bidirectional data bus ?
The following is the code of my bidirectional receiver ...
ENTITY bidir IS
PORT(
bidir : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
oe, clk : IN STD_LOGIC;
inp : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
outp : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END bidir;
ARCHITECTURE Behave OF bidir IS
SIGNAL a : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores
-- value from input.
SIGNAL b : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores
BEGIN -- feedback value.
bidir <=a when oe = '1' else (others => 'Z');
PROCESS(clk)
BEGIN
IF clk = '1' AND clk'EVENT THEN -- Creates the flipflops
a <= inp;
b <= bidir;
outp <= b;
END IF;
END PROCESS;
End behave;