Interfacing Wishbone Bus with UART

[dragonvnu]

Hi all !
I have to interface Wishbone Bus and UART, I use the Wishbone_conmax architecture to connect the WIshbone and UART and I use their IP Cores from OpenCores.org .
However, my problem is that I do not understand the way to interfacing and I don't have any knowledge regarding a bout UART module.
Can anyone explain for me to solve this project or guide for me from design block, analysis and implementation of IP core based on VHDL ? I need some VHDL code examples for my project.

THanks all !

 

[harerama]

Hi..I also try to do on Wishbone_conmax architecture shel i join with you.If you intrested please contact My mail id is ragufedora@gamil.com