Yes of course, it has to be continuous access. The datasheet says CE doesn't toggle for continuous access, so I guess I should have no problem. However, I'm still finding the addressing issue for this parallel NOR a little bit cumbersome. Take the 2Gb device (dual die) as an example. The datasheet says the memory array is made of 2048 uniform blocks, 128KB each. With that being said, only 2048 locations are being addressed in order to read/write to the chip. So, why and how the full 25 address lines are utilized here?