grubby23
Junior Member level 3
Hi,
I would like to interface my FPGA design with a SRAM chip. I looked at a related .ucf file which uses this SRAM chip and there it said:
NET sram_clk IOSTANDARD = LVCMOS33;
NET sram_clk DRIVE=16;
NET sram_clk SLEW=FAST;
...
NET sram_addr(*) IOSTANDARD = LVDCI_33;
NET sram_addr(*) DRIVE=8;
NET sram_addr(*) FAST;
Normally, I simply used the constraint file for port mapping, so could somebody please quickly explain me what is the slew and drive here? Why do I use one drive=16 and the other time drive = 8? Furthermore, where do I find out what is the IOSTANDARD, is this to be found in the SRAM documentation?
Many thanks for your input
I would like to interface my FPGA design with a SRAM chip. I looked at a related .ucf file which uses this SRAM chip and there it said:
NET sram_clk IOSTANDARD = LVCMOS33;
NET sram_clk DRIVE=16;
NET sram_clk SLEW=FAST;
...
NET sram_addr(*) IOSTANDARD = LVDCI_33;
NET sram_addr(*) DRIVE=8;
NET sram_addr(*) FAST;
Normally, I simply used the constraint file for port mapping, so could somebody please quickly explain me what is the slew and drive here? Why do I use one drive=16 and the other time drive = 8? Furthermore, where do I find out what is the IOSTANDARD, is this to be found in the SRAM documentation?
Many thanks for your input