Interfacing SPARTAN 3 with DDR SDRAM + MIG_V2.3 problem

error:constraintsystem:59

Hi,

I am trying to Interface DDR SDRAM with Spartan3. I am using MIG_V2.3 to generate Interface block.

When I am doing PAR, I am getting the following error.....
-----------------------------------------------------------------------------------------------
Resolving constraint associations...
Checking Constraint Associations...
ERROR:ConstraintSystem:58 - Constraint <NET
"top_00/data_path0/data_read_controller0/gen_wr_addr*fifo*_wr_addr_inst/clk"
TNM_NET = "fifo_waddr_clk";> [DDRSDRAM.ucf(44)]: NET
"top_00/data_path0/data_read_controller0/gen_wr_addr*fifo*_wr_addr_inst/clk"
does not match any design objects.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_WADDR_CLK" = FROM
"dqs_clk" TO "fifo_waddr_clk" 5 ns DATAPATHONLY;> [DDRSDRAM.ucf(45)]: Unable
to find an active 'TimeGrp' or 'TNM' or 'TPSync' or 'TPThru' constraint named
'fifo_waddr_clk'.

ERROR:ConstraintSystem:59 - Constraint <INST
"infrastructure_top0/cal_top0/cal_ctl0" AREA_GROUP = cal_ctl;>
[DDRSDRAM.ucf(293)]: INST "infrastructure_top0/cal_top0/cal_ctl0" not found.
Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

ERROR:ConstraintSystem:59 - Constraint <INST
"infrastructure_top0/cal_top0/tap_dly0" AREA_GROUP = cal_ctl;>
[DDRSDRAM.ucf(294)]: INST "infrastructure_top0/cal_top0/tap_dly0" not found.
Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

WARNING:ConstraintSystem:56 - Constraint <AREA_GROUP "cal_ctl" RANGE =
SLICE_X74Y4:SLICE_X85Y17;> [DDRSDRAM.ucf(295)]: Unable to find an active
'Area_Group' constraint named 'cal_ctl'.

WARNING:ConstraintSystem:56 - Constraint <AREA_GROUP "cal_ctl" GROUP = CLOSED;>
[DDRSDRAM.ucf(296)]: Unable to find an active 'Area_Group' constraint named
'cal_ctl'.
-----------------------------------------------------------------------------------------------
With out modification of UCF and .VHD code.... I am getting like this error.

Can you tell me why it is showing error like this.

I found that this problem is arising where ever "gen_wr_addr*fifo*_wr_addr_inst" presents in the UCF.