Interfacing small modules to main module in vhdl structural modeling

[Swathi k]

Hi,
I am swathi doing my M.tech final project on BIST and I am using BISR technique.It contains MUX,memory,BIST and BIAA modules.I got the output for individual blocks but when I am trying to use them in main module output goes wrong.I used clk in some processes and without clk in some other processes.BIAA module has to store fault address in a memory.It works gud wen used alone but wen it is interfaced with remaining fault memory shows previous addresses otherthan fault locations.Can anybody please answer this?

 

[TrickyDicky]

Have you got a testbench? are you debugging in a simulator?

 

[Swathi k]

i did with testbench only.but i dont know how to debug.can u please tell me how to debug the code?can we see the output for each and every line in output window?I dont know how to use step icon

 

[TrickyDicky]

You can put all signals from within the design onto the waveform window. If you are using modelsim, make sure you invoke vsim with the novopt switch:

vsim -novopt my_top_level

 

[Swathi k]

Thank you
I am using xilinx ise9.2i.The problem is I have used clk in some processes and didnt use clk in others.so wen I am simulating the top module the processses with clk are executing correctly but the remaining are not.As a result the output goes wrong.The processes with out clk are giving correcr output wen executing individually but the problem is with top module implementation.can help?

 

[TrickyDicky]

It sounds like incorrect implementation, rather than something "not working".

You need a top level testbench. Why not post some code thats "not working"

 

[Swathi k]

Here is the brief explanation of my project.(Efficient built in self repair strategy for embedded SRAM using selectable redundancy)
The project deals with testing of a memory before using it. The memory contains 64 locations(6 address lines),4bit data in it.6 redundancy locations for reparing purpose.(58 to 63 are redundancy locations).To test the memory locations it uses BIST.BIST internally contains TPG (uses MarchC-algorithm)and ORA(comparator).

---Test_h=1,bisr_h=0(testing but not reparing)

Testing involves writing and reading alternate zeros and ones in all memory locations and comparing the read data with expected data. Inputs to the memory are from MUX module, which is able to apply either test inputs (during testing operation) or normal inputs(from user) depending on the selection lines. ORA produces compare_q=’ if the read data from memory is not equal to expected data. BIAA module stores the corresponding address location in a memory called fault memory whenever it receives compare_q=1 signal from BIST.BIST produces test_done=1 when it executes all march elements(1 to 6).This indicates testing is completed .At this time fault memory in BIAA contains all fault locations in the memory. (up to 6 faults are acceptable).If the faults are more than 6 over_flow=1.

---Test_h=1, bisr_h=1(checking redundancy locations)

It checks whether the fault memory contains faults greater than 57 r not. Greater than 57 indicate that faults in redundancy locations. It makes fail_h=1 indicating repairing is not possible.

---Test_h=0,bisr_h=1

Now if we activate normal operation by making test_h=0 and bisr_h=1(i.e;no testing but repairing ) if we give address, data, wen(write enable), cen (chip enable) to the mux, it connects these to the memory and memory writes the data whatever we have given in the corresponding address location in general but here ,before applying the address to the address line of the memory, BIAA checks the address with all the addresses in fault memory.(means it checks whether it is equal to fault location)If it finds it in the fault memory ,as repairing is activated it produces repaired address to the memory.(eg,after testing is completed consider the fault locations are 3,8,10. Now in normal operation the user inputs are address=8, data=13, wen=1, cen=1.BIAA checks and changes address into one of the redundancy locations. To do this it follows one to one mapping.i.e;
Location of the fault in fault memory corresponding one to one mapping
1 63
2 62
3 61
4 60
5 59
6 58
So in our eg,it finds 8 in 2nd location so the address changed to 62
After repairing the inputs to the memory are
---Writing:
Address=62(after reparing), data=13, wen=1, cen=1 and the operation will be performed. Now if we want to read the data from the same location
---Reading:
Address=8, wen=0, cen=1.Again as repairing is activated the procedure follows and address becomes 62 so we got the correct data 13 as output.

----Test_h=0,bisr_h=0(no testing,no reparing)
--Writing:
Address=8, data=13, wen=1, cen=1.
biaa won’t check and address is 8 only and data stores in that.
---Reading: when we try to read the data by giving address=8, wen=0,cen=1 it comes out from 8th location but not from 62nd location so we will get wrong output.

- - - Updated - - -

MUX module code:selects inputs to the memory between user inputs and test inputs
----------------------------------------------------------------------------------

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity mux_main is
    Port ( NA,TA : in  STD_LOGIC_VECTOR (5 downto 0);
           ND,TD : in  STD_LOGIC_VECTOR (3 downto 0);
           NWEN,TWEN,NCEN,TCEN,test_h : in  STD_LOGIC;
           address_out : out  STD_LOGIC_VECTOR (5 downto 0);
           data_out : out  STD_LOGIC_VECTOR (3 downto 0);
           wen_out,cen_out : out  STD_LOGIC);
end mux_main;
 
architecture Behavioral of mux_main is
component mux2to1_address_sel
    Port ( TA,NA : in  STD_LOGIC_VECTOR (5 downto 0);
           s : in  STD_LOGIC;
           address_out : out  STD_LOGIC_VECTOR (5 downto 0));
end component;
component mux2to1_data_sel
    Port ( TD,ND : in  STD_LOGIC_VECTOR (3 downto 0);
           S : in  STD_LOGIC;
           data_out : out  STD_LOGIC_VECTOR (3 downto 0));
end component;
component mux2to1_wen
    Port ( TWEN,NWEN : in  STD_LOGIC;
           S : in  STD_LOGIC;
           wen_out : out  STD_LOGIC);
end component;
component mux2to1_cen
    Port ( NCEN,TCEN : in  STD_LOGIC;
           S : in  STD_LOGIC;
           cen_out : out  STD_LOGIC);
end component;
begin
m1:mux2to1_address_sel port map(ta=>ta,na=>na,s=>test_h,address_out=>address_out);
m2:mux2to1_data_sel port map(td=>td,nd=>nd,s=>test_h,data_out=>data_out);
m3:mux2to1_wen port map(twen=>twen,nwen=>nwen,s=>test_h,wen_out=>wen_out);
m4:mux2to1_cen port map(tcen=>tcen,ncen=>ncen,s=>test_h,cen_out=>cen_out);
end Behavioral;

---

-------------------------------------test bench------------------------------

--------------------------------------------------------------------------------

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY tb_mux_main_vhd IS
END tb_mux_main_vhd;
 
ARCHITECTURE behavior OF tb_mux_main_vhd IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT mux_main
    PORT(
        NA : IN std_logic_vector(5 downto 0);
        TA : IN std_logic_vector(5 downto 0);
        ND : IN std_logic_vector(3 downto 0);
        TD : IN std_logic_vector(3 downto 0);
        NWEN : IN std_logic;
        TWEN : IN std_logic;
        NCEN : IN std_logic;
        TCEN : IN std_logic;
        test_h : IN std_logic;          
        address_out : OUT std_logic_vector(5 downto 0);
        data_out : OUT std_logic_vector(3 downto 0);
        wen_out : OUT std_logic;
        cen_out : OUT std_logic
        );
    END COMPONENT;
 
    --Inputs
    SIGNAL NWEN :  std_logic := '0';
    SIGNAL TWEN :  std_logic := '0';
    SIGNAL NCEN :  std_logic := '0';
    SIGNAL TCEN :  std_logic := '0';
    SIGNAL test_h :  std_logic := '0';
    SIGNAL NA :  std_logic_vector(5 downto 0) := (others=>'0');
    SIGNAL TA :  std_logic_vector(5 downto 0) := (others=>'0');
    SIGNAL ND :  std_logic_vector(3 downto 0) := (others=>'0');
    SIGNAL TD :  std_logic_vector(3 downto 0) := (others=>'0');
 
    --Outputs
    SIGNAL address_out :  std_logic_vector(5 downto 0);
    SIGNAL data_out :  std_logic_vector(3 downto 0);
    SIGNAL wen_out :  std_logic;
    SIGNAL cen_out :  std_logic;
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
    uut: mux_main PORT MAP(
        NA => NA,
        TA => TA,
        ND => ND,
        TD => TD,
        NWEN => NWEN,
        TWEN => TWEN,
        NCEN => NCEN,
        TCEN => TCEN,
        test_h => test_h,
        address_out => address_out,
        data_out => data_out,
        wen_out => wen_out,
        cen_out => cen_out
    );
test_h<='1' after 100 ns;
--cen<='1';
    tb : PROCESS
    BEGIN
        ta<="101100";
        td<="1111";
        twen<='1';
        tcen<='1';
        na<="000111";
        nd<="0111";
        nwen<='1';
        ncen<='1';
        wait for 50 ns;
        ta<="111111";
        td<="1100";
        twen<='1';
        tcen<='1';
        na<="001101";
        nd<="0101";
        nwen<='0';
        ncen<='0';
        wait for 50 ns;
       ta<="101100";
        td<="1111";
        twen<='1';
        tcen<='1';
        na<="000111";
        nd<="0111";
        nwen<='1';
        ncen<='1';
        
        wait; 
    END PROCESS;
 
END;

---

-----------------------------memory module code and test bench-----------------------
----------------------------------------------------------------------------------

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:53:58 03/26/2014 
-- Design Name: 
-- Module Name:    memory - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity memory is
    Port ( address : in  STD_LOGIC_VECTOR (5 downto 0);
           data_in : in  STD_LOGIC_VECTOR (3 downto 0);
           wen,cen,clk : in  STD_LOGIC;
           data_out_q : out  STD_LOGIC_VECTOR (3 downto 0));
end memory;
 
architecture Behavioral of memory is
type mem is ARRAY(0 to 63)of std_logic_vector(3 downto 0);
signal mem_ptr:mem;
constant fault1:std_logic_vector(3 downto 0):="1010";
constant fault2:std_logic_vector(3 downto 0):="0000";
constant fault3:std_logic_vector(3 downto 0):="1100";
begin
process(clk)
begin
if(clk'event and clk = '1')then
    if(cen='1')then
        if(wen='1')then
            mem_ptr(conv_integer(address))<=data_in;        --writing operation
           mem_ptr(3)<=fault1;                                  --considered fault address as 3rd location and data in that
         mem_ptr(5)<=fault2;        
            mem_ptr(9)<=fault3;
        end if;                                         --is 10.it wont store data_in.it stores 10 always
    end if;
end if;
end process;
process(address)
begin
if(cen='1')then
    if(wen='0')then
        data_out_q<=mem_ptr(conv_integer(address));
    end if;
end if;
end process;    
end Behavioral;

---

-------------testbench---------------
--------------------------------------------------------------------------------

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use ieee.std_logic_arith.all;
 
ENTITY tb_memory_vhd IS
END tb_memory_vhd;
 
ARCHITECTURE behavior OF tb_memory_vhd IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT memory
    PORT(
        address : IN std_logic_vector(5 downto 0);
        data_in : IN std_logic_vector(3 downto 0);
        wen : IN std_logic;
        cen : IN std_logic;
        clk : IN std_logic;          
        data_out_q : OUT std_logic_vector(3 downto 0)
        );
    END COMPONENT;
 
    --Inputs
    SIGNAL wen :  std_logic := '0';
    SIGNAL cen :  std_logic := '0';
    SIGNAL clk :  std_logic := '0';
    SIGNAL address :  std_logic_vector(5 downto 0) := (others=>'0');
    SIGNAL data_in :  std_logic_vector(3 downto 0) := (others=>'0');
 
    --Outputs
    SIGNAL data_out_q :  std_logic_vector(3 downto 0);
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
    uut: memory PORT MAP(
        address => address,
        data_in => data_in,
        wen => wen,
        cen => cen,
        clk => clk,
        data_out_q => data_out_q
    );
clk<=not clk after 10 ns;
 
    tb : PROCESS
    BEGIN
    wen<='1';
    cen<='1';
 
    for i in 0 to 9 loop
    address<=address+'1';
    data_in<="0000";
 
    wait for 20  ns;
    end loop;
    wen<='0';
 
    for i in 0 to 9 loop
    address<=address-'1';
    wait for 20 ns;
    end loop;
    END PROCESS;
 
END;

---

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
--------------------marchC- algorithm code and test bench-------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity marchcfor2elements is
    Port ( test_h,clk,rst_l : in  STD_LOGIC;
            data_in_ora:in std_logic_vector(3 downto 0);
           ta : out  STD_LOGIC_VECTOR (5 downto 0);
           td : out  STD_LOGIC_VECTOR (3 downto 0);
           twen,tcen,compare_q,test_done,test_phase : out std_logic);
end marchcfor2elements;
architecture Behavioral of marchcfor2elements is
signal s:std_logic_vector(5 downto 0):=(others=>'0');
signal march:std_logic_vector(2 downto 0):="001";
signal op:std_logic;
begin
process(clk)
begin
if (rst_l='0')then
    ta<="000000";
    td<="0000";
    tcen<='0';
    twen<='0';
elsif(clk'event and clk='1')then
    if(test_h='1')then
        test_phase<='1';
        if(march="001")then                                 --march element1 up(w0)
            ta<=s;
            td<="0000";
            twen<='1';
            tcen<='1';
            if(s="111111") then
                march<="010";
                s<="000000";
                op<='0';
            else
                s<=s+'1';
            end if;
        elsif(march="010")then                                  --march element2 up(r0,w1)
            if(s="111111")then
                if(op='0')then                                  
                    ta<=s;
                    td<="XXXX";
                    twen<='0';
                    tcen<='1';
                    op<='1';
                elsif(op='1')then
                    ta<=s;
                    td<="1111";
                    twen<='1';
                    tcen<='1';
                    march<="011";
                    s<="000000";
                    op<='0';
                end if;
            else 
                if(op='0')then                                  
                    ta<=s;
                    td<="XXXX";
                    twen<='0';
                    tcen<='1';
                    op<='1';
                elsif(op='1')then
                    ta<=s;
                    td<="1111";
                    twen<='1';
                    tcen<='1';
                    op<='0';
                    s<=s+'1';
                end if; 
            end if;
        elsif(march="011")then                                  --march element3 up(r1,w0)
            if(s="111111")then
                if(op='0')then                                  
                    ta<=s;
                    td<="XXXX";
                    twen<='0';
                    tcen<='1';
                    op<='1';
                elsif(op='1')then
                    ta<=s;
                    td<="0000";
                    twen<='1';
                    tcen<='1';
                    march<="100";
                    op<='0';
                end if;
            else
                if(op='0')then                                  
                    ta<=s;
                    td<="XXXX";
                    twen<='0';
                    tcen<='1';
                    op<='1';
                elsif(op='1')then
                    ta<=s;
                    td<="0000";
                    twen<='1';
                    tcen<='1';
                    op<='0';
                    s<=s+'1';
                end if; -- op
            end if;     -- s
        elsif(march="100")then                                  --march element4 down(r0,w1)
            if(s="000000")then
                if(op='0')then                                  
                    ta<=s;
                    td<="XXXX";
                    twen<='0';
                    tcen<='1';
                    op<='1';
                elsif(op='1')then
                    ta<=s;
                    td<="1111";
                    twen<='1';
                    tcen<='1';
                    op<='0';
                    march<="101";
                    s<="111111";
                    op<='0';
                end if;
            end if;
            if(op='0')then                                  
                ta<=s;
                td<="XXXX";
                twen<='0';
                tcen<='1';
                op<='1';
            elsif(op='1')then
                ta<=s;
                td<="1111";
                twen<='1';
                tcen<='1';
                op<='0';
                s<=s-'1';
            end if;                 
        elsif(march="101")then                                  --march element5 down(r1,w0)
            if(s="000000")then
                if(op='0')then                                  --some doubt elsif or if?
                    ta<=s;
                    td<="XXXX";
                    twen<='0';
                    tcen<='1';
                    op<='1';
                elsif(op='1')then
                    ta<=s;
                    td<="0000";
                    twen<='1';
                    tcen<='1';
                    march<="110";
                    s<="111111";
                    op<='0';
                end if;
            end if;
            if(op='0')then                                  --some doubt elsif or if?
                ta<=s;
                td<="XXXX";
                twen<='0';
                tcen<='1';
                op<='1';
            elsif(op='1')then
                ta<=s;
                td<="0000";
                twen<='1';
                tcen<='1';
                op<='0';
                s<=s-'1';
            end if;
        elsif(march="110")then                                  --march element6 down(r0)
            if(s="000000")then
               march<="111";
            end if;                            
            ta<=s;
            td<="XXXX";
            twen<='0';
            tcen<='1';
            op<='1';
            s<=s-'1';
        elsif(march="111")then
            test_done<='1';
      else
            test_done<='0';               
        end if; --march
    end if; --test_h
end if; --rstl
end process;
 
--comparing :ORA part in BIST   
process(data_in_ora,march)
begin
if(march="010")then
   if(op='1')then 
        if(data_in_ora="0000")then
            compare_q<='0';
        else
            compare_q<='1';
        end if;
    end if; 
elsif(march="011")then
    if(op='1')then 
        if(data_in_ora="1111")then
            compare_q<='0';
        else
            compare_q<='1';
        end if;
    end if;
elsif(march="100")then
   if(op='1')then 
        if(data_in_ora="0000")then
            compare_q<='0';
        else
            compare_q<='1';
        end if; 
    end if;
elsif(march="101")then
   if(op='1')then 
        if(data_in_ora="1111")then
            compare_q<='0';
        else
            compare_q<='1';
        end if; 
    end if;
elsif(march="110")then
   if(op='1')then 
        if(data_in_ora="0000")then
            compare_q<='0';
        else
            compare_q<='1';
        end if; 
    end if;
end if; 
end process;
end Behavioral;         
 
 
------------testbench------
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY tb_marchcfor2elements_vhd IS
END tb_marchcfor2elements_vhd;
 
ARCHITECTURE behavior OF tb_marchcfor2elements_vhd IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT marchcfor2elements
    PORT(
        test_h : IN std_logic;
        clk : IN std_logic;
        rst_l : IN std_logic;
        data_in_ora : IN std_logic_vector(3 downto 0);          
        ta : OUT std_logic_vector(5 downto 0);
        td : OUT std_logic_vector(3 downto 0);
        twen : OUT std_logic;
        tcen : OUT std_logic;
        compare_q : OUT std_logic;
        test_done : OUT std_logic;
        test_phase : OUT std_logic
        );
    END COMPONENT;
 
    --Inputs
    SIGNAL test_h :  std_logic := '0';
    SIGNAL clk :  std_logic := '0';
    SIGNAL rst_l :  std_logic := '0';
    SIGNAL data_in_ora :  std_logic_vector(3 downto 0) := (others=>'0');
 
    --Outputs
    SIGNAL ta :  std_logic_vector(5 downto 0);
    SIGNAL td :  std_logic_vector(3 downto 0);
    SIGNAL twen :  std_logic;
    SIGNAL tcen :  std_logic;
    SIGNAL compare_q :  std_logic;
    SIGNAL test_done :  std_logic;
    SIGNAL test_phase :  std_logic;
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
    uut: marchcfor2elements PORT MAP(
        test_h => test_h,
        clk => clk,
        rst_l => rst_l,
        data_in_ora => data_in_ora,
        ta => ta,
        td => td,
        twen => twen,
        tcen => tcen,
        compare_q => compare_q,
        test_done => test_done,
        test_phase => test_phase
    );
clk<=not clk after 20 ns;
rst_l<='1';
test_h<='1';
    tb : PROCESS
    BEGIN
 
    data_in_ora<="1010";    -- Wait 100 ns for global reset to finish
        wait for 2677.4 ns;
data_in_ora<="0000";
wait for 100 ns;
data_in_ora<="1100";
 
        -- Place stimulus here
 
        wait; -- will wait forever
    END PROCESS;
 
END;
 
 
-----------------biaa code and testbench-------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity biaa is
    Port ( compare_q,test_phase,bisr_h,test_h : in  STD_LOGIC;
           ta,bisr_a : in  STD_LOGIC_VECTOR (5 downto 0);
           over_h_reg,fail: out  STD_LOGIC;
           biaa_out_ad : out  STD_LOGIC_VECTOR (5 downto 0));
end biaa;
 
architecture Behavioral of biaa is
type fault_a_mem is array(0 to 5)of std_logic_vector(5 downto 0);
signal fa_ptr:fault_a_mem;
type repair_mem is array(0 to 5)of std_logic_vector(5 downto 0);
signal rep_ptr:repair_mem;
signal address:std_logic_vector(2 downto 0):=(others=>'0');
signal count:std_logic_vector(2 downto 0):="000";
signal c:std_logic;
begin
      rep_ptr(0)<=conv_std_logic_vector(63,6);
      rep_ptr(1)<=conv_std_logic_vector(62,6);
      rep_ptr(2)<=conv_std_logic_vector(61,6);
      rep_ptr(3)<=conv_std_logic_vector(60,6);
      rep_ptr(4)<=conv_std_logic_vector(59,6);
      rep_ptr(5)<=conv_std_logic_vector(58,6);     
process(compare_q,test_h,bisr_h)
begin   
if(compare_q='1')then
    fa_ptr(conv_integer(address))<=ta;
    address<=address+'1';
    if(address="000101")then
    fa_ptr(conv_integer(address))<=ta;
       address<="000";
        over_h_reg<='1';
    end if;
end if;
--if(commpare_q='0')then
if(test_h='0')then                                          --normal operation without testing and repairing
  if(bisr_h='0')then
    biaa_out_ad<=bisr_a;
        elsif(bisr_h='1')then                               --repairing operation
            for i in 0 to 5 loop
                if(bisr_a=fa_ptr(i))then
                    biaa_out_ad<=rep_ptr(i);
                        else
                        biaa_out_ad<=bisr_a;
                end if; 
            end loop;   
    end if;
end if;
if(test_h='1')then                                          --testing without repairing 
    if(bisr_h='0')then
      for i in 0 to 5 loop
        if (bisr_a=fa_ptr(i))then
            biaa_out_ad<=fa_ptr(i);
       else
            biaa_out_ad<=bisr_a;
        end if;
     end loop;      
    elsif(bisr_h='1')then                                   --testing redundancy locations
            for i in 0 to 5 loop
              if(bisr_a=rep_ptr(i))then
                fail<='1';
                 else 
                    fail<='0';
              end if; 
            end loop;
    end if;
end if;
--end if;   
--end if;       
end process;
end Behavioral;
 
----testbench-------
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_arith.ALL;
 
ENTITY tb_biaa_vhd IS
END tb_biaa_vhd;
 
ARCHITECTURE behavior OF tb_biaa_vhd IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT biaa
    PORT(
        compare_q : IN std_logic;
        test_phase : IN std_logic;
        bisr_h : IN std_logic;
        test_h : IN std_logic;
        ta : IN std_logic_vector(5 downto 0);
        bisr_a : IN std_logic_vector(5 downto 0);          
        over_h_reg : OUT std_logic;
        fail : OUT std_logic;
        biaa_out_ad : OUT std_logic_vector(5 downto 0)
        );
    END COMPONENT;
 
    --Inputs
    SIGNAL compare_q :  std_logic := '0';
    SIGNAL test_phase :  std_logic := '0';
    SIGNAL bisr_h :  std_logic := '0';
    SIGNAL test_h :  std_logic := '0';
    SIGNAL ta :  std_logic_vector(5 downto 0) := (others=>'0');
    SIGNAL bisr_a :  std_logic_vector(5 downto 0) := (others=>'0');
 
    --Outputs
    SIGNAL over_h_reg :  std_logic;
    SIGNAL fail :  std_logic;
    SIGNAL biaa_out_ad :  std_logic_vector(5 downto 0);
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
    uut: biaa PORT MAP(
        compare_q => compare_q,
        test_phase => test_phase,
        bisr_h => bisr_h,
        test_h => test_h,
        ta => ta,
        bisr_a => bisr_a,
        over_h_reg => over_h_reg,
        fail => fail,
        biaa_out_ad => biaa_out_ad
    );
--compare_q<=not compare_q after 10 ns;
--compare_q<='1';
    tb : PROCESS
    BEGIN
compare_q<='1';
ta<=conv_std_logic_vector(50,6);
wait for 10 ns;
ta<=conv_std_logic_vector(30,6);
wait for 10 ns;
ta<=conv_std_logic_vector(20,6);
wait for 10 ns;
ta<=conv_std_logic_vector(10,6);
wait for 10 ns;
ta<=conv_std_logic_vector(11,6);
wait for 10 ns;
ta<=conv_std_logic_vector(12,6);
wait for 10 ns;
compare_q<='0';
test_h<='0';
bisr_h<='0';
bisr_a<=conv_std_logic_vector(12,6);
wait for 10 ns;
bisr_a<=conv_std_logic_vector(22,6);
wait for 10 ns;
bisr_h<='1';
bisr_a<=conv_std_logic_vector(50,6);
wait for 10 ns;
bisr_a<=conv_std_logic_vector(30,6);
wait for 10 ns;
bisr_a<=conv_std_logic_vector(19,6);
wait for 10 ns;
bisr_a<=conv_std_logic_vector(11,6);
wait for 10 ns;
bisr_a<=conv_std_logic_vector(18,6);
wait for 10 ns;
test_h<='1';
bisr_h<='0';
bisr_a<=conv_std_logic_vector(25,6);
wait for 10 ns; 
bisr_a<=conv_std_logic_vector(35,6);
wait for 10 ns;
bisr_a<=conv_std_logic_vector(50,6);
wait for 10 ns; 
bisr_a<=conv_std_logic_vector(30,6);
wait for 10 ns; 
bisr_a<=conv_std_logic_vector(29,6);
wait for 10 ns; 
bisr_h<='1';
bisr_a<=conv_std_logic_vector(62,6);
wait for 10 ns;
bisr_a<=conv_std_logic_vector(57,6);
wait for 10 ns; 
bisr_a<=conv_std_logic_vector(53,6);
wait for 10 ns; 
----end if; 
END PROCESS;
 
END;
 
 
----------main module--------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity interfacing1 is
    Port ( test_h,clk,rst_l : in  STD_LOGIC;
           na : in  STD_LOGIC_VECTOR (5 downto 0);
           nd : in  STD_LOGIC_VECTOR (3 downto 0);
           nwen : in  STD_LOGIC;
           ncen : in  STD_LOGIC;
           data_out_q : out  STD_LOGIC_VECTOR (3 downto 0);
           compare_q ,test_done: out  STD_LOGIC);
end interfacing1;
 
architecture Behavioral of interfacing1 is
signal bm_ta,mm_ad :std_logic_vector(5 downto 0);
signal bm_td,mm_data,mb_data :std_logic_vector(3 downto 0);
signal bm_twen,bm_tcen,mm_wen,mm_cen: std_logic;
component mux_main 
     Port ( NA,TA : in  STD_LOGIC_VECTOR (5 downto 0);
           ND,TD : in  STD_LOGIC_VECTOR (3 downto 0);
           NWEN,TWEN,NCEN,TCEN,test_h : in  STD_LOGIC;
           address_out : out  STD_LOGIC_VECTOR (5 downto 0);
           data_out : out  STD_LOGIC_VECTOR (3 downto 0);
           wen_out,cen_out : out  STD_LOGIC);
end component;
component memory
     Port ( address : in  STD_LOGIC_VECTOR (5 downto 0);
           data_in : in  STD_LOGIC_VECTOR (3 downto 0);
           wen,cen,clk : in  STD_LOGIC;
           data_out_q : out  STD_LOGIC_VECTOR (3 downto 0));
end component;
component march_c_1
     Port ( test_h,clk,rst_l : in  STD_LOGIC;
            data_in_ora:in std_logic_vector(3 downto 0);
           ta : out  STD_LOGIC_VECTOR (5 downto 0);
           td : out  STD_LOGIC_VECTOR (3 downto 0);
           twen,tcen,compare_q,test_done : out  STD_LOGIC); 
end component;
begin
m1:mux_main port map(na=>na,nd=>nd,nwen=>nwen,ncen=>ncen,
                     ta=>bm_ta,td=>bm_td,twen=>bm_twen,tcen=>bm_tcen,
                            test_h=>test_h,
                            address_out=>mm_ad,data_out=>mm_data,
                            wen_out=>mm_wen,cen_out=>mm_cen);
--m1:mux_main port map(na,bm_ta,nd,bm_td,nwen,bm_twen,ncen,bm_tcen,test_h,mm_ad,mm_data,mm_wen,mm_cen);
--mem:memory port map(mm_ad,mm_data,mm_wen,mm_cen,clk,mb_data);
--mar:march_c_1 port map(test_h,clk,rst_l,mb_data,bm_ta,bm_td,bm_twen,bm_tcen,compare_q);
mem:memory port map(address=>mm_ad,data_in=>mm_data,wen=>mm_wen,cen=>mm_cen,
                          clk=>clk,data_out_q=>mb_data);
mar:march_c_1 port map(test_h=>test_h,clk=>clk,rst_l=>rst_l,
                              data_in_ora=> mb_data,
                       compare_q=>compare_q,test_done=>test_done,
                              ta=>bm_ta,td=>bm_td,twen=>bm_twen,tcen=>bm_tcen);
                       
end Behavioral;
 
-testbench------------to test only test_h=1,bisr_h=0
 
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_arith.ALL;
 
 
ENTITY tb_interfacing1_vhd IS
END tb_interfacing1_vhd;
 
ARCHITECTURE behavior OF tb_interfacing1_vhd IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT interfacing1
    PORT(
        test_h : IN std_logic;
        clk : IN std_logic;
        rst_l : IN std_logic;
        na : IN std_logic_vector(5 downto 0);
        nd : IN std_logic_vector(3 downto 0);
        nwen : IN std_logic;
        ncen : IN std_logic;          
        data_out_q : OUT std_logic_vector(3 downto 0);
        compare_q : OUT std_logic;
        test_done:out std_logic
        );
    END COMPONENT;
 
    --Inputs
    SIGNAL test_h :  std_logic := '0';
    SIGNAL clk :  std_logic := '0';
    SIGNAL rst_l :  std_logic := '0';
    SIGNAL nwen :  std_logic := '0';
    SIGNAL ncen :  std_logic := '0';
    SIGNAL na :  std_logic_vector(5 downto 0) := (others=>'0');
    SIGNAL nd :  std_logic_vector(3 downto 0) := (others=>'0');
 
    --Outputs
    SIGNAL data_out_q :  std_logic_vector(3 downto 0);
    SIGNAL compare_q :  std_logic;
    SIGNAL test_done :  std_logic;
 
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
    uut: interfacing1 PORT MAP(
        test_h => test_h,
        clk => clk,
        rst_l => rst_l,
        na => na,
        nd => nd,
        nwen => nwen,
        ncen => ncen,
        data_out_q => data_out_q,
        compare_q => compare_q,
        test_done=>test_done
    );
clk<=not clk after 10 ns;
    tb : PROCESS
    BEGIN
--rst_l<='0';
--wait for 10 ns;
test_h<='1';
rst_l<='1';
wait for 10 ns;
if(test_done='1')then
test_h<='0';
na<=conv_std_logic_vector(15,6);
nd<="0100";
nwen<='1';
ncen<='1';
wait for 20 ns;
nwen<='0';
na<=conv_std_logic_vector(3,6);
wait for 20 ns;
na<=conv_std_logic_vector(15,6);
wait for 20 ns;
na<=conv_std_logic_vector(6,6);
wait for 20 ns;
end if;
END PROCESS;
 
END;

---

for individual modules i got the write output but wen I am implementing it goes wrong .Please help

 

[TrickyDicky]

Im not surprised - there are many many bugs:

- Memory: This has an asynchronous read port - therefore cannot be mapped to a memory - this will be built from logic (and latches at that)

- marchcfor2elements: first of all, reset is missing from the first process sensitivity list, so async reset will not work in simulation.
-2nd process: op missing from sensitivity list. Also, this process will produce latches on real hardware as definition is imcomplete (you did not assign all signals in ALL cases)
- biaa: again, many missing signals from sensitivity lists and latches are going to get formed.

So many many areas where the simulation behavior is not going to match the real hardware. Simulation needs correct sensitivity lists - synthesis will ignore them. This will lead to missmatches.

I suggest reviewing your code, fixing these bugs, and try re-simulating.

 

[Swathi k]

Thank you for ur reply.What are the signals to be include in the sensitivity list?
As the address to the memory is from biaa module,it is clock based but wen,cen,data are applied to the memory wenever they comeout from the mux and address is applied the address lines of the memory after one clockpulse.can i delay the wen,cen,data from assigning to the memory

 

[ads-ee]

Thank you for ur reply.What are the signals to be include in the sensitivity list?

Include all signals that are read in a process. (e.g. signals on the RHS of assignments, in the if expression, etc)

As the address to the memory is from biaa module,it is clock based but wen,cen,data are applied to the memory wenever they comeout from the mux and address is applied the address lines of the memory after one clockpulse.can i delay the wen,cen,data from assigning to the memory

If they aren't liked up then you should delay them with respect to the address so they arrive a the same time as the address. (um, you know this is pretty basic stuff when pipelining hardware designs).

Regards