r_p_sanna
Member level 3
Any body help me out how to interface matlab model in Verilog.
The objective is like I have a matlab model which gets the input from the verilog and generates output. Verilog needs to use the Matlab output for further processing.
The objective is like I have a matlab model which gets the input from the verilog and generates output. Verilog needs to use the Matlab output for further processing.