Interfacing Freescale MPC to FPGA (input/output delay constraints)

[rku]

I am trying to interface a Freescale microcontroller (MPC) with FPGA. MPC has an external bus interface (EBI) with EBI clock (CLKOUT) which can be used by the FPGA. All control/address/data signals of MPC (TS, TA, CS, RDWR, ADDR, DATA etc.) are output by MPC wrt the CLKOUT signal. The FPGA is sampling the MPC control/address/data signals also wrt to its CLKOUT input clock.

The question is, do I need to specify input/output delay constraints for the MPC control/address/data signals wrt CLKOUT in the FPGA? If yes, how can calculate the delay value? The Freescale datasheet says the maximum output delay of the control/data/address signals wrt to CLKOUT is 6ns.

Do I also need to consider the PCB and PAD delays of FPGA, as all the signals viz. CLKOUT and control/address/data signals, are routed directly from MPC? The PCB and PAD delays on those signals, including the clock (CLKOUT), are assumed to be alsmost equal.

NB: CLKOUT clock input is buffered and used internally in FPGA. It is not connected to any PLL.

Thank you.

 

[ads-ee]

The question is, do I need to specify input/output delay constraints for the MPC control/address/data signals wrt CLKOUT in the FPGA? If yes, how can calculate the delay value? The Freescale datasheet says the maximum output delay of the control/data/address signals wrt to CLKOUT is 6ns.

You didn't define what the CLKOUT frequency was, and I'm not going to go download the MPC data sheet (which there might be a whole family of devices with different speed grades).

If the frequency is 1 MHz then you probably don't need to have input output constraints, just receive everything on the opposite edge of the clock wrt the MPC and transmit on the opposite edge that the MPC receives. If you have a CLKOUT frequency that is approaching 166 MHz then you won't be able to find any constraints that will work (unless the FPGA provides some method of clock/data skew control). So those are the two extreme options given that we don't know anything about the actual interface frequency and/or the FPGA device/speed you are using.

Do I also need to consider the PCB and PAD delays of FPGA, as all the signals viz. CLKOUT and control/address/data signals, are routed directly from MPC? The PCB and PAD delays on those signals, including the clock (CLKOUT), are assumed to be alsmost equal.

Once again you don't provide enough information. If the timing is extremely close even 10's of ps delay differences might be a problem.

NB: CLKOUT clock input is buffered and used internally in FPGA. It is not connected to any PLL.

Given that you've buffered it and we don't know the device, who knows what the delay between the internal clock tree reaching the input register and the data arrival time to the register are.

Seems to me you need to brush up on calculating timing budgets for digital designs.

 

[rku]

First of all, thank you ads-ee for the reply and I appologise for the amount of ambiguity in my question.

Seems to me you need to brush up on calculating timing budgets for digital designs

I am relatively new to STA and am just trying to learn.

The CLKOUT frequency of the Freescale processor is 64MHz (MPC5566 operating at 128MHz). The FPGA being used in the design is Actel ProASIC3L (speed grade: std).
In the current design, the FSMs in the FPGA are receiving the signals from MPC at the same rising edge at which MPC is driving.