interfacing FPGA and DDR3

[hannachifaten]

Hello everybody!



I'm planning to use DDR3 RAM with Spartan 6, my configuration for MIG is one 32 bit input port and one 32 bit output port. I'm looking for simple example how to properly connect signals from generated MCB to the rest of my logic in VHDL and also how to properly use MCB to efficiently read and write data.
- i generate MCB using MIG xilinx , but i need some help some direction to use it in my top programe
- i guess that i use the instantion template in the top code but i'm not sure ,

Thanks for any help

 

[Ishaan Karnik]

This is the user guide hope you may may fing it useful
https://www.xilinx.com/support/documentation/user_guides/ug388.pdf

 

[hannachifaten]

This is the user guide hope you may may fing it useful
https://www.xilinx.com/support/documentation/user_guides/ug388.pdf

thank you ,
i read it , but my problem is in the VHDL code , how to use :
i have a programme after that i add core MIG to add the MCB
I used the instantiation of the core i cpoie the component and i paste it in the top programme ,
after that i dont know how can i interface with DDR3 , to write and read from it ?
SO i need a simple sequence of work , that all
any seggetion please

 

[TrickyDicky]

The specs and timing diagrams are all in that documentation.

 

[izhar hussain sherazi]

hello any body can share some data about mechanical encoders

 

[TrickyDicky]

Why not try starting your own thread in a more appropriate forum?

 

[hannachifaten]

hello again ,
i have to write into the DDR3 but until know i don't find how , i'm sory im biggner , but i write a code VHDL to write in Ram memory , i want to know how to write the same thing but using DDR3 with the MIG tools , please any help
any example guid me ?
i know that is very easy for you but i'm trainee student ,
thanks

 

[TrickyDicky]

How about looking at a reference design:
**broken link removed**

 

[hannachifaten]

How about looking at a reference design:
**broken link removed**

thank you for your reply , but a have a lot of documentation , my question is : after using the memory interfac generator and getting the files of the mig , and having differents out in puts of MCB and the Input of DDR ....
how can i implement this all files ( from core generator) to my top programme which is writing data from FPGA to DDR3 , how to integrate all this , i tried to developp a new source where i integrate the componnant of MCB and the different signals , an i write process of Writing data to ram like this but usually i guess that is wrong :/
entity top-level is


port (

data_in : in unsigned(8 - 1 downto 0); -- 8 bit data
address : in unsigned(8 - 1 downto 0):= (others => '0'); -- 8 bit add
we : in std_logic; -- write enable
data_out : out unsigned(8 - 1 downto 0)

);




--! DDR RAM device ports
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
rzq3 : inout std_logic;
zio3 : inout std_logic;
mcb3_dram_udm : out std_logic;

mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_clk : out std_logic;
mcb3_dram_clk_n : out std_logic

);
end data_write ;

architecture Behavioral of data_write is

type mem_type is array (2**8 downto 0) of unsigned(8 - 1 downto 0); -- 256 ram deep and 8 bits wide
signal mem : mem_type; --declaring the memory

begin
memory : process (we,address,mem,data_in)
begin

if (we = '1') then
mem(to_integer(address)) <= data_in; -- write
end if ;

data_out <= mem(to_integer(address)); -- read

end process memory;



--! MCB control signals

signal c3_sys_clk : std_logic;
signal c3_sys_rst_i : std_logic;
signal c3_calib_done : std_logic;
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;

signal c3_p2_cmd_clk : std_logic;
signal c3_p2_cmd_en : std_logic;
signal c3_p2_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p2_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p2_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p2_cmd_empty : std_logic;
signal c3_p2_cmd_full : std_logic;

signal c3_p2_wr_clk : std_logic;
signal c3_p2_wr_en : std_logic;
signal c3_p2_wr_mask : std_logic_vector(3 downto 0);
signal c3_p2_wr_data : std_logic_vector(31 downto 0);
signal c3_p2_wr_full : std_logic;
signal c3_p2_wr_empty : std_logic;
signal c3_p2_wr_count : std_logic_vector(6 downto 0);
signal c3_p2_wr_underrun : std_logic;
signal c3_p2_wr_error : std_logic;

signal c3_p3_cmd_clk : std_logic;
signal c3_p3_cmd_en : std_logic;
signal c3_p3_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p3_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p3_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p3_cmd_empty : std_logic;
signal c3_p3_cmd_full : std_logic;

signal c3_p3_rd_clk : std_logic;
signal c3_p3_rd_en : std_logic;
signal c3_p3_rd_data : std_logic_vector(31 downto 0);
signal c3_p3_rd_full : std_logic;
signal c3_p3_rd_empty : std_logic;
signal c3_p3_rd_count : std_logic_vector(6 downto 0);
signal c3_p3_rd_overflow : std_logic;
signal c3_p3_rd_error : std_logic;


component ddr3
generic(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3000;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 3
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk_p : in std_logic;
c3_sys_clk_n : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_wr_clk : in std_logic;
c3_p2_wr_en : in std_logic;
c3_p2_wr_mask : in std_logic_vector(3 downto 0);
c3_p2_wr_data : in std_logic_vector(31 downto 0);
c3_p2_wr_full : out std_logic;
c3_p2_wr_empty : out std_logic;
c3_p2_wr_count : out std_logic_vector(6 downto 0);
c3_p2_wr_underrun : out std_logic;
c3_p2_wr_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_rd_clk : in std_logic;
c3_p3_rd_en : in std_logic;
c3_p3_rd_data : out std_logic_vector(31 downto 0);
c3_p3_rd_full : out std_logic;
c3_p3_rd_empty : out std_logic;
c3_p3_rd_count : out std_logic_vector(6 downto 0);
c3_p3_rd_overflow : out std_logic;
c3_p3_rd_error : out std_logic;
c3_p4_cmd_clk : in std_logic;
c3_p4_cmd_en : in std_logic;
c3_p4_cmd_instr : in std_logic_vector(2 downto 0);
c3_p4_cmd_bl : in std_logic_vector(5 downto 0);
c3_p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p4_cmd_empty : out std_logic;
c3_p4_cmd_full : out std_logic;
c3_p4_wr_clk : in std_logic;
c3_p4_wr_en : in std_logic;
c3_p4_wr_mask : in std_logic_vector(3 downto 0);
c3_p4_wr_data : in std_logic_vector(31 downto 0);
c3_p4_wr_full : out std_logic;
c3_p4_wr_empty : out std_logic;
c3_p4_wr_count : out std_logic_vector(6 downto 0);
c3_p4_wr_underrun : out std_logic;
c3_p4_wr_error : out std_logic;
c3_p5_cmd_clk : in std_logic;
c3_p5_cmd_en : in std_logic;
c3_p5_cmd_instr : in std_logic_vector(2 downto 0);
c3_p5_cmd_bl : in std_logic_vector(5 downto 0);
c3_p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p5_cmd_empty : out std_logic;
c3_p5_cmd_full : out std_logic;
c3_p5_rd_clk : in std_logic;
c3_p5_rd_en : in std_logic;
c3_p5_rd_data : out std_logic_vector(31 downto 0);
c3_p5_rd_full : out std_logic;
c3_p5_rd_empty : out std_logic;
c3_p5_rd_count : out std_logic_vector(6 downto 0);
c3_p5_rd_overflow : out std_logic;
c3_p5_rd_error : out std_logic
);
end component;


------------------------------------------------------------------------------------------
------------- ARCHITECTURE BEGIN ---------------------
------------------------------------------------------------------------------------------

begin

u_ddr3 : ddr3
generic map (
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C3_SIMULATION => C3_SIMULATION,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH
)
port map (

c3_sys_clk_p => c3_sys_clk_p,
c3_sys_clk_n => c3_sys_clk_n,
c3_sys_rst_i => c3_sys_rst_i,

mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
c3_clk0 => c3_clk0,
c3_rst0 => c3_rst0,


c3_calib_done => c3_calib_done,
mcb3_rzq => rzq3,

mcb3_zio => zio3,
c3_p0_cmd_clk => c3_p0_cmd_clk,
c3_p0_cmd_en => c3_p0_cmd_en,
c3_p0_cmd_instr => c3_p0_cmd_instr,
c3_p0_cmd_bl => c3_p0_cmd_bl,
c3_p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
c3_p0_cmd_empty => c3_p0_cmd_empty,
c3_p0_cmd_full => c3_p0_cmd_full,
c3_p0_wr_clk => c3_p0_wr_clk,
c3_p0_wr_en => c3_p0_wr_en,
c3_p0_wr_mask => c3_p0_wr_mask,
c3_p0_wr_data => c3_p0_wr_data,
c3_p0_wr_full => c3_p0_wr_full,
c3_p0_wr_empty => c3_p0_wr_empty,
c3_p0_wr_count => c3_p0_wr_count,
c3_p0_wr_underrun => c3_p0_wr_underrun,
c3_p0_wr_error => c3_p0_wr_error,
c3_p0_rd_clk => c3_p0_rd_clk,
c3_p0_rd_en => c3_p0_rd_en,
c3_p0_rd_data => c3_p0_rd_data,
c3_p0_rd_full => c3_p0_rd_full,
c3_p0_rd_empty => c3_p0_rd_empty,
c3_p0_rd_count => c3_p0_rd_count,
c3_p0_rd_overflow => c3_p0_rd_overflow,
c3_p0_rd_error => c3_p0_rd_error,
c3_p1_cmd_clk => c3_p1_cmd_clk,
c3_p1_cmd_en => c3_p1_cmd_en,
c3_p1_cmd_instr => c3_p1_cmd_instr,
c3_p1_cmd_bl => c3_p1_cmd_bl,
c3_p1_cmd_byte_addr => c3_p1_cmd_byte_addr,
c3_p1_cmd_empty => c3_p1_cmd_empty,
c3_p1_cmd_full => c3_p1_cmd_full,
c3_p1_wr_clk => c3_p1_wr_clk,
c3_p1_wr_en => c3_p1_wr_en,
c3_p1_wr_mask => c3_p1_wr_mask,
c3_p1_wr_data => c3_p1_wr_data,
c3_p1_wr_full => c3_p1_wr_full,
c3_p1_wr_empty => c3_p1_wr_empty,
c3_p1_wr_count => c3_p1_wr_count,
c3_p1_wr_underrun => c3_p1_wr_underrun,
c3_p1_wr_error => c3_p1_wr_error,
c3_p1_rd_clk => c3_p1_rd_clk,
c3_p1_rd_en => c3_p1_rd_en,
c3_p1_rd_data => c3_p1_rd_data,
c3_p1_rd_full => c3_p1_rd_full,
c3_p1_rd_empty => c3_p1_rd_empty,
c3_p1_rd_count => c3_p1_rd_count,
c3_p1_rd_overflow => c3_p1_rd_overflow,
c3_p1_rd_error => c3_p1_rd_error,
c3_p2_cmd_clk => c3_p2_cmd_clk,
c3_p2_cmd_en => c3_p2_cmd_en,
c3_p2_cmd_instr => c3_p2_cmd_instr,
c3_p2_cmd_bl => c3_p2_cmd_bl,
c3_p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
c3_p2_cmd_empty => c3_p2_cmd_empty,
c3_p2_cmd_full => c3_p2_cmd_full,
c3_p2_wr_clk => c3_p2_wr_clk,
c3_p2_wr_en => c3_p2_wr_en,
c3_p2_wr_mask => c3_p2_wr_mask,
c3_p2_wr_data => c3_p2_wr_data,
c3_p2_wr_full => c3_p2_wr_full,
c3_p2_wr_empty => c3_p2_wr_empty,
c3_p2_wr_count => c3_p2_wr_count,
c3_p2_wr_underrun => c3_p2_wr_underrun,
c3_p2_wr_error => c3_p2_wr_error,
c3_p3_cmd_clk => c3_p3_cmd_clk,
c3_p3_cmd_en => c3_p3_cmd_en,
c3_p3_cmd_instr => c3_p3_cmd_instr,
c3_p3_cmd_bl => c3_p3_cmd_bl,
c3_p3_cmd_byte_addr => c3_p3_cmd_byte_addr,
c3_p3_cmd_empty => c3_p3_cmd_empty,
c3_p3_cmd_full => c3_p3_cmd_full,
c3_p3_rd_clk => c3_p3_rd_clk,
c3_p3_rd_en => c3_p3_rd_en,
c3_p3_rd_data => c3_p3_rd_data,
c3_p3_rd_full => c3_p3_rd_full,
c3_p3_rd_empty => c3_p3_rd_empty,
c3_p3_rd_count => c3_p3_rd_count,
c3_p3_rd_overflow => c3_p3_rd_overflow,
c3_p3_rd_error => c3_p3_rd_error,
c3_p4_cmd_clk => c3_p4_cmd_clk,
c3_p4_cmd_en => c3_p4_cmd_en,
c3_p4_cmd_instr => c3_p4_cmd_instr,
c3_p4_cmd_bl => c3_p4_cmd_bl,
c3_p4_cmd_byte_addr => c3_p4_cmd_byte_addr,
c3_p4_cmd_empty => c3_p4_cmd_empty,
c3_p4_cmd_full => c3_p4_cmd_full,
c3_p4_wr_clk => c3_p4_wr_clk,
c3_p4_wr_en => c3_p4_wr_en,
c3_p4_wr_mask => c3_p4_wr_mask,
c3_p4_wr_data => c3_p4_wr_data,
c3_p4_wr_full => c3_p4_wr_full,
c3_p4_wr_empty => c3_p4_wr_empty,
c3_p4_wr_count => c3_p4_wr_count,
c3_p4_wr_underrun => c3_p4_wr_underrun,
c3_p4_wr_error => c3_p4_wr_error,
c3_p5_cmd_clk => c3_p5_cmd_clk,
c3_p5_cmd_en => c3_p5_cmd_en,
c3_p5_cmd_instr => c3_p5_cmd_instr,
c3_p5_cmd_bl => c3_p5_cmd_bl,
c3_p5_cmd_byte_addr => c3_p5_cmd_byte_addr,
c3_p5_cmd_empty => c3_p5_cmd_empty,
c3_p5_cmd_full => c3_p5_cmd_full,
c3_p5_rd_clk => c3_p5_rd_clk,
c3_p5_rd_en => c3_p5_rd_en,
c3_p5_rd_data => c3_p5_rd_data,
c3_p5_rd_full => c3_p5_rd_full,
c3_p5_rd_empty => c3_p5_rd_empty,
c3_p5_rd_count => c3_p5_rd_count,
c3_p5_rd_overflow => c3_p5_rd_overflow,
c3_p5_rd_error => c3_p5_rd_error
);



end behavior;


is it wrong i know

 

[TrickyDicky]

You really are best looking at reference designs. All the source code will be there for you to look at,

 

[hannachifaten]

You really are best looking at reference designs. All the source code will be there for you to look at,

THANK YOU , i have ISE14.2 , so i don't find reference design for this version , thanks ,
i didn' find any example

 

[mew2sharan]

The files will be generated inside the "ipcore_dir" under your project folder. You'll've rtl files inside those folders. Add them and use

 

[hannachifaten]

thank you, so could you tell me if i'm in the right way or not :
- i start new project , a i add new source "interface.vhd" where i use the interface with DDR and how i can write ( like i write in the Ram )
- I create a core generator with MIG i create MCB bloc : many files are added in "ipcore-dir" also an IP core is added in my hierarchy
- after that i instantiate this core with "View HDL instantiation " and i paste it the component in my source which is "interface.vhd" i complete the differeents signal
-and my question now is if : i add the different files in "ipcore-dir " with "add copie source" and i add only the rtl files in my project or not , ( i want exactly know how to use this files ) and if i'm getting the right way or not in this creation of project ,

 

[syedshan]

Hi

After you genertate the core.
Look at the folders and there you will find an example design and theri respective readme files.

The example design (with all the RTL + simulation codes will be there) is the best to start at.
Once you find it.
Make a new project.
add all those files, (there will be folders like RTL, sim, etc. etc.) even subfolders.

Once this is done then try running the simulation.
If you are really a begineer you will get few errors like dont have this file or that file etc. but this will help to learn as well as to proceed further in this project.

Try running this simulation and then write back

btw my experience (underway) is with virtex-6 and DDR3 (I amsuing ug406) as a reference what are you using