Chip select, read and write enable address and data lines are usually sufficient optionally byte enables, wait, and a memory clock.
The most interesting point is how the FPGA and processor clock domains are coordinate and how to assure consistent data transfers in both directions. The best solution depends much on the FPGA application details like datapath toplogy need for simultaneous access to registers, clock rates, if the FPGA clock can be derived from the ARM core clock.
For this reasons there's no simple answer of "do this" or "do that".