I'm new in mc68000. This is a very good CPU.
I desing one board and build it. But not work.
The CPU steps eight clock cycle and stop with active _HALT signal.
Generating rom select and ram select and other selects from a21-a22-a23 and _AS with 74hc138.
Generating _DTACK from 74hc138 Yn with 74hc07.
Generating _BERR from _E divided by eight and inverted. Divider reseted by _AS.
I double-triple checked all chip(include 27c64 contents and test ram chips).
Select signals works perfectly, but CPU ends operating in eighth of clk cycle.
How to generate right _BERR and _dtack signal?
Please help!